Abstract: In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

Abstract: A data carrier (1) for contactless communication comprises a first carrier layer (2) and a second carrier layer (3) which are held together by an adhesive layer (15), wherein an integrated circuit (11) is held in a given position between one of the two carrier layers (2, 3) and the adhesive layer (15), the circuit comprising transmission means (13, 14) which can communicate in a contactless manner with transmission means (7, 8) at the carrier layer, and the transmission means (7, 8) of the carrier layer are connected with electrical conduction to further transmission means (5, 6) by which a contactless communication with a communication station can be carried out, and wherein the final, mechanically stable retention of the integrated circuit (11) in the position reserved for it in the data carrier (1) is realized by means of the adhesive layer (15) only.

Abstract: A flip-chip package uses a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature that is an expected operating temperature of the chip. The elevated temperature can be the midpoint of the desired temperature cycle of the chip so that deformations of the electrical connections in one direction balance deformations in the opposite direction during temperature cycling. Matching spacing at an elevated temperature, even a temperature less than the bonding temperature, permits a better alignment at the bonding temperature for formation of stronger bonds.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: In a COC type semiconductor device, a bump electrode of a second semiconductor chip is joined to a first semiconductor chip having a bump electrode formed thereon. The bump electrodes and of the respective first and second semiconductor chips and are both made of first metal such as Au having a relatively high melting point, while a joining portion of these bump electrodes and is formed of an alloy layer of the first metal and second metal, which second metal is made of such a material that can melt at a lower temperature than the melting point of the first metal to be alloyed with it. As a result, in the COC type semiconductor device, when interconnecting a plurality of semiconductor chips, their electrode terminals can be joined to each other without deteriorating the properties of these chips owing to the high temperature applied thereon.

Abstract: An optical semiconductor device having a low threshold current and easiness of a single transverse mode oscillation is provided. The optical semiconductor device has a low device parasitic capacitance that allows a direct modulation at high speed. The optical semiconductor device comprises a first conduction type substrate, a stripe shaped active layer formed on the first conduction type substrate, a mesa shaped burying layer formed around the active layer and having a larger band gap than that of the active layer, and a groove that electrically isolates the burying layer, wherein the section of the burying layer is in an inverse trapezoid shape of which the upper base side is longer than the lower base side.

Abstract: The invention relates to a packaging for a semiconductor chip. A frame that directly surrounds the slot is provide on the carrier board on the side of the nubbins. Said frame is provided with the same height as the nubbins and the slot and the frame surrounding said slot are at least partially filled with a casting compound which is preferably adapted to the thermal expansion coefficients of the semiconductor chip.

Abstract: Metal layer in a semiconductor device and method for fabricating the same, the semiconductor device having a transistor and a capacitor electrode formed on a region of a semiconductor substrate, the metal layer including a planar protection film on an entire surface of the semiconductor substrate inclusive of the transistor and the capacitor electrode, an absorber layer over the planar protection film inclusive of a region over the transistor, an insulating film on an entire surface, with a width of projection in a relievo form in a region over the absorber layer, a via hole through the planar protection film and the insulating layer, to expose a region of the capacitor electrode, a tungsten plug and a planar stuffed layer in the via hole, a mirror metal layer on the insulating film on both sides of the projection of a relievo form of the insulating film, inclusive of the planar stuffed layer, and an insulating film spacer on the projection of a relievo form of the insulating film and the mirror metal layer i

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A stacked multi-chip semiconductor package and a fabrication method thereof are provided. A chip carrier is formed with an opening for receiving a first chip therein, and a second chip is stacked on the first chip and over the opening, wherein the first and second chips are respectively electrically connected to the chip carrier by bonding wires. A first encapsulant is formed to encapsulate first chip and corresponding bonding wires, and a second encapsulant is formed around the second chip to encompass a cavity for receiving the second chip and corresponding bonding wires therein. A lid is attached to the second encapsulant for covering the cavity. This semiconductor package allows high integration and increase in operational performances by virtue of stacked multi-chip structure.

Abstract: A light emitting device includes a semiconductor light emitting element and a silicone resin provided to embed said semiconductor light emitting element, where silicone resin has a hardness not lower than 50 in JISA value. The use of a silicone resin as the resin for sealing the semiconductor light emitting elements instead of conventional epoxy resins can reduce the possibility of cracks, exfoliation, breakage of wire, etc. that were often caused by conventional epoxy resins, and can also improve the resistance to whether and light.

Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

Abstract: A frame for semiconductor packages has die-pads supported with suspending leads of individual lead frames. Semiconductor devices are mounted on the respective die-pads. These semiconductor devices are collectively molded with molding compound, and then the collectively molded semiconductor packages are cut into individual packages by means of a dicing saw. In the frame, thin parts are formed in areas corresponding to the roots of individual terminals, the thin parts being formed by half-etching metal of the areas from the front or back thereof. Alternatively, hollows are formed in areas corresponding to the roots of individual terminals.

Abstract: The present invention relates to a photodiode of an image sensor. Particularly, the photodiode is formed on a substrate so that an occupying area of a unit pixel of the image sensor is reduced.

Abstract: A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Abstract: A semiconductor device which satisfies both the requirements for radiation performance and for miniaturization while having a semiconductor element for a heavy current. The semiconductor device has an IGBT element (1) and diode element (2) which are provided on the main surface of the heat spreader (25) in a strip form formed of a metal with excellent heat conductivity and electricity conductivity. In addition, a relay terminal block (20) is provided outside of the IGBT element (1) on the main surface of the heat spreader (25) and the relay terminal block (20), the IGBT element (1) and the diode element (2) are aligned. Then, the external connection electrode plates (81) and (82) are, respectively, provided on both sides of this alignment.

Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

Abstract: A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer.

Abstract: The invention concerns a semiconductor power element (diode 18) having a lead (11) and a safety fuse (12) situated in the main current path that blows when overheated, particularly for use in the electrical system of motor vehicles. In order to achieve a previously determined, purposeful disconnection of the endangered element in order to avoid consequential damages when semiconductor power elements become overloaded, it is proposed that a segment (11b) of the lead (11) and/or its points of contact in the main current path of the semiconductor be designed as a safety fuse (12) that blows when a specified, current-dependent temperature value is reached.

Abstract: Integrated circuit (IC) package structures and IC package fabrication techniques are provided. The IC package substrate is formed from a metal sheet that is patterned to form a substrate with pads and leads. These pads and leads are pattered throughout the substrate including at least part of the die mounting area. The die is mounted onto the die mounting area of the lead-frame, and respective bonding terminals on the die are electrically connected to the associated bonding areas on the patterned leads. A protective encapsulant is molded to cover the die, bond wires, and most, if not all, of the patterned substrate. Contacts for external electrical connection are formed onto the bottom of the pads.