Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract: The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals.

Abstract: An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.

Abstract: A semiconductor device of the invention comprises a semiconductor element provided within a housing, a bonding wire, a sealing resin member covering the semiconductor element and bonding wire, and a sheet member. The sheet member is fixed in the housing and arranged out of contact with the bonding wire, and moreover buried in the sealing resin member. Because the sheet member restrains the sealing resin member from vibrating, the bonding wire is connected with improved reliability. In place of the sheet member, it is possible to use a pillar member fixed on an insulating substrate. The semiconductor device is suitable for use on a mobile body, such as a vehicle, which proceeds with vibrations.

Abstract: A protective sheet is fixed to a jig, and regions of the protective sheet corresponding to regions where dicing-cut is to be performed are removed to form grooves. Then, a semiconductor wafer is bonded to the protective sheet at an opposite side of the jig, and the jig is detached from the protective sheet and the semiconductor wafer bonded together. After that, the semiconductor wafer is cut into semiconductor chips by dicing along the grooves of the protective sheet. Because the protective sheet is not cut by dicing, no scraps of the protective sheet is produced, thereby preventing contamination to the chips.

Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.

Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

Abstract: A lighted sign having raised letters or other shapes. The letters are lighted from within and have more than one color visible from the outside of the letter. Each letter has a peripheral translucent wall of a first color and a translucent face plate of a second color. An LED holding frame is held within the peripheral wall and has LED's of the same color as the face plate held within the peripheral wall. At the back of the peripheral wall LEDs of a color the same as the peripheral side wall are held.

Abstract: A semiconductor structure and a method of determining an overlay error produced during formation of the semiconductor structure are disclosed. The semiconductor structure comprises a first two-dimensional periodic pattern and a second two-dimensional periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second two-dimensional periodic patterns indicates the magnitude and direction of an overlay error caused during the formation of the first and second two-dimensional periodic patterns. The semiconductor allows one to independently determine the overlay errors in linearly independent directions by directing a light beam of known optical properties onto the first and second two-dimensional periodic patterns and by analyzing the diffracted beam by comparison with reference data.

Abstract: Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.

Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.

Abstract: A sputter target is made of a Ti—Al alloy containing Al in the range of 1 to 30 atm %. In the Ti—Al alloy constituting the sputter target, Al exists in at least one of a solid solution state in Ti and a state in which Al forms an intermetallic compound with Ti, and variation in Al content in the entire target is limited within 10%. Furthermore, an average crystal grain diameter of the Ti—Al alloy is 500 &mgr;m or less, and variation in crystal grain diameter in the entire target is limited within 30%. A Ti—Al—N film as a barrier film is formed by using the sputter target made of the Ti—Al alloy as described above. An electronic component includes a barrier film formed on a semiconductor substrate.

Abstract: A metallization system (10) suitable for use in a semiconductor component and a method for fabricating the metallization system (10). The metallization system (10) includes a dielectric material (20) disposed on a major surface (14) of a substrate (12). The dielectric material (20) contains a dielectric filled plug (26) over a conductor (19). A metal filled plug (38) extends through the dielectric filled plug (26). The metal of the metal filled plug (38) electrically contacts the conductor (19). The metallization system (10) may be fabricated by etching a via (24) in the dielectric material (20) and filling the via (24) with a dielectric material (26) having a dielectric constant that is greater than the dielectric constant of the dielectric material (20) disposed on the major surface. A via (34) is formed in the dielectric material (26) that fills the via (24) and the via (34) is filled with a metal.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A first insulation layer 33 is embedded between adjacent ones of the fuses 20. A second insulation layer 39 is formed on the first insulation layer 33. The first insulation layer 33 and the second insulation layer 39 are formed such that their interface 42 is generally at the same level as the top surface of the fuses 20. As a result, the fuses may be reliably fused without generating cracks in the interface 42 at the time of fusing the fuses.

Abstract: A wiring substrate has signal transmission paths in a strip line structure implemented through sandwiching of signal wiring layers between first and second conductor layers via first and second dielectric layers. Through holes are formed in the first conductor layer. The through holes are not formed in wiring correspondence regions, which correspond to the signal wiring layers as projected onto the first conductor layer in the thickness direction of the first conductor layer. All of the through holes are formed in a wiring noncorrespondence region, which is the remaining portion of the first conductor layer not including the wiring correspondence regions.

Abstract: A substrate has a pair of metal bases, and a first heat insulation layer disposed between the metal bases. A second heat insulation layer is securely mounted on the metal bases, and a pair of circuit patterns are securely mounted on the second heat insulation layer for mounting an LED.

Abstract: Described is an electronic device having a compliant fibrous interface. The interface comprises a free fiber tip structure having flocked thermally conductive fibers embedded in an adhesive in substantially vertical orientation with portions of the fibers extending out of the adhesive and an encapsulant between the portions of the fibers that extend out of the adhesive and the fiber's free tips.