Abstract: A resonant-cavity light-emitting diode includes a semiconductor light-emitting layer sandwiched between an under and an upper semiconductor distributed Bragg reflector mirror layer, which are formed on the substrate, a light extracting section formed on the upper semiconductor distributed Bragg reflector mirror layer and having an opening to extract light from the semiconductor light-emitting layer, and a groove formed by removing portions of the semiconductor light-emitting layer, under and upper semiconductor distributed Bragg reflector mirror layers which lie in a peripheral portion of the opening of the light extraction section and reach the under semiconductor distributed Bragg reflector mirror layer, the inner wall of the groove being formed to reflect part of light emitted from the semiconductor light-emitting layer into the groove.

Abstract: An illuminator includes a first terminal, a second terminal, and a light emitting diode mounted on the first terminal and electrically connected to the second terminal. The light emitting diode includes a chip body, a lower electrode formed on a lower surface of the chip body, and an upper electrode formed on an upper surface of the chip body. The chip body includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer interposed therebetween. The upper electrode is formed entirely over the upper surface of the chip electrode.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: Disclosed is a thin film deposition apparatus for depositing a thin film on a display panel including a deposition source having a groove in one surface wherein the groove is filed with a thin film material to be deposited on the panel, a heater applying heat to the deposition source so as to sublimate the thin film material, and a mask loaded on the deposition source so as to cover the groove of the deposition source, the mask having a plurality of holes to adjust a deposition quantity of the thin film material deposited on the panel.

Abstract: A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution.

Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.

Abstract: A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element (53, 153, 203) is coupled between the first and second contact elements (51, 151, 201). At least a majority of the fusing element (53, 153, 203) comprises silicided material.

Abstract: A method and structure for a semiconductor structure that includes a substrate having at least one integrated circuit heat generating structure is disclosed. The invention has at least one integrated circuit cooling device on the substrate adjacent the heat generating structure. The cooling device is adapted to remove heat from the heat generating structure. The cooling device includes a cold region and a hot region. The cold region is positioned adjacent the heat generating structure. The cooling device has one of a silicon germanium super lattice structure. The cooling device also has a plurality of cooling devices that surround the heat generating structure. The cooling device includes a thermoelectric cooler.

Abstract: A surface mount ceramic package, e.g. for a microwave or millimeter wave integrated circuit device, has outer conductive pads that are available for direct connection with traces on the printed circuit board. A metal core or base has spaces at one or more sides, e.g., voids or cutouts, where the outer pads are located. There is a first ceramic layer disposed on the core, with a central cavity for the die, and an upper or second ceramic layer. Printed traces are buried between the two layers, and vias connect the traces with the outer pads. Inner pads are located on a ledge of the first layer adjacent the cavity for connection with electrodes of the die. Each of the first and second ceramic layers may be stacked ceramic tape. The package may be LTCC or HTCC. This construction avoids inductive losses, especially at higher frequencies.

Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.

Abstract: A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle inter-level insulating film and the conductive layer. The upper inter-level insulating film includes first, second, and third wiring grooves distant from each other. The second and third wiring grooves use the conductive layer as their bottoms. The side surfaces of the first, second, and third wiring grooves are covered with in-groove barrier layers. First, second, and third wiring layers are buried in the first, second, and third wiring grooves. The first, second, and third wiring layers are derived from the same wiring film, and have a thickness larger than that of the conductive layer. The second and third wiring layers are electrically connected to the conductive layer.

Abstract: This invention relates to organic based spintronic devices, and electronic devices comprising them, including spin valves, spin tunnel junctions, spin transistors and spin light-emitting devices. New polymer-, organic- and molecular-based electronic devices in which the electron spin degree of freedom controls the electric current to enhance device performance. Polymer-, organic-, and molecular-based spintronic devices have enhanced functionality, ease of manufacture, are less costly than inorganic ones. The long spin coherence times due to the weak spin-orbit interaction of carbon and other low atomic number atoms that comprise organic materials make them ideal for exploiting the concepts of spin quantum devices. The hopping mechanism of charge transport that dominates in semiconducting polymers (vs. band transport in crystalline inorganic semiconductors) enhances spin-magneto sensitivity and reduces the expected power loss.

Abstract: A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 120 degree bump placement structures is provided.

Abstract: A semiconductor device 1000 in accordance with the present invention has a structure having multiple wiring layers, and includes a bonding pad 40a, dummy wiring forming regions 35 including dummy wirings 30, and dummy wiring prohibiting regions 15 where dummy wirings are not formed. The dummy wiring prohibiting regions 15 are provided at least below a region where the bonding pad 40a is formed.

Abstract: An organic light emitting diode (OLED) device. The OLED device comprises a transparent substrate, a plurality of anodes, an organic functional layer, a black layer and a plurality of cathodes. The anodes are positioned over a transparent substrate. The organic function layer is positioned over the transparent substrate covering the anodes. The black layer is positioned over the organic functional layer and the cathodes are positioned over the black layer. Through the black layer, the amount of back reflection of external light is reduced and the contrast of the display device is increased.

Abstract: An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Abstract: The present invention provides a semiconductor device having a substrate on which a plurality of semiconductor chips are stacked, wherein the semiconductor device comprising; a first semiconductor chip mounted on the substrate, a plurality of second semiconductor chips size of which are larger than that of the first semiconductor chip and stacked on the first semiconductor chip with a size-increasing order, a bonding pad formed on the semiconductor chip, a circuit pattern formed on the substrate, a bonding wire for connecting the bonding pad formed on the semiconductor chip and the circuit pattern formed on the substrate, a through hole, formed on the substrate, through which the bonding wire is to be inserted, and further wherein the bonding wire is wired so as to be substantially perpendicularly to a surface of the semiconductor chip.

Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.

Abstract: An integrated circuit package including a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer. A copper leadframe is fixed to the flexible circuit tape and electrically isolated from the conductor layer. The copper leadframe includes an etched down die attach pad and heat spreader portions. The die attach pad is etched down such that at least a portion of the die attach pad is reduced in thickness. The through holes in the flexible circuit tape extend through to the copper leadframe. A semiconductor die is mounted on the at least a portion of the die attach pad. Wire bonds extend from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer, an encapsulating material encapsulates the semiconductor die and the wire bonds.

Abstract: Semiconductor packages including at least one semiconductor chip and at least one electronic discrete device, such as a transistor, oscillator, optical sensor, resistor, capacitor, or inductor, are disclosed. The semiconductor chip and the discrete device are electrically coupled to each other, and are encapsulated within a protective encapsulant material. The semiconductor chip and the discrete device are disposed either in an aperture through the substrate or in a pocket of the substrate, thereby allowing for a thin package, even where the discrete device is taller (e.g., 1.5 to 5 times taller) than the semiconductor chip and/or substrate.