Abstract: A non-rectangular thermo module is formed by disposing a plurality of Peltier devices between a pair of heat radiating plates, wherein the heat radiating plate has a circular or straight outer peripheral contour portion and inner peripheral contour portion and right/left side edge contour portions connecting the outer peripheral contour portion and the inner peripheral contour portion and the outer peripheral contour portion is formed longer than the inner peripheral contour portion while the right/left side edge contour portions contain first straight lines which are not parallel and inclined toward the inner peripheral contour portion such that they narrow gradually, the first straight lines being provided at least in part of the right/left side edge contour portions.

Abstract: The invention concerns a light emitting and guiding device comprising at least one active region (22) in silicon and the means for creating photons in the said active region. In accordance with the invention, the means for creating the photons comprise a diode (22c, 22d) formed in the active region. In addition, the device includes the means for confining the carriers injected by the diode, and the silicon in the active region is mono-crystalline.

Abstract: Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

Abstract: There is provided an electronic device comprising at least one electronic part and a substrate on which said electronic part is mounted, said electronic part and said substrate being bonded by a joint comprising a phase of Al particles and another phase of a Al—Mg—Ge—Zn alloy, said Al particles being connected to each other by said Al—Mg—Ge—Zn alloy phase.

Abstract: A connection structure is configured such that electrodes formed on an overcoat layer on a substrate are connected to other electrode terminals using an anisotropically electroconductive adhesive 30 comprising electroconductive particles dispersed in an insulating adhesive, wherein the angle of encroachment A of the electroconductive particles 32 into the overcoat layer 4 is made to be at least 135°.

Abstract: A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air vent in a mold. After a semiconductor chip is mounted on the substrate by a plurality of conductive elements, a molding compound having high fluidity and fine filler particles is used to encapsulate the chip and the flash preventing mechanism. As the flash preventing mechanism is disposed in a manner of reducing the entry space of the air vent, the flow of the molding compound is impeded by the flash preventing mechanism, making the molding compound rapidly absorb heat of the mold and accordingly increased in viscosity. This helps prevent flash of the molding compound from occurrence, and assure the semiconductor package in quality and profile.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are electrically connected to the nodes. A multimedia chip has an active surface and a corresponding back surface, and a plurality of bonding pads are formed on the active surface of the multimedia chip. The back surface of the multimedia chip is adhered on the die pad of the substrate unit. A molding compound encapsulates the multimedia chip, the first surface of the substrate unit, and the conductive wires, and exposes the second surface of the substrate unit and the external nodes.

Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants less than about 3.0, with some materials having dielectric constants less than about 2.5. Integrated circuit devices, integrated circuit packaging devices, and methods of manufacture are provided as well.

Abstract: An integrated circuit package is described that includes a capacitor structure having a pair of plates separated by a dielectric material. An integrated circuit (IC) die is carried by a top surface of the first capacitor plate. The die carried by the capacitor structure is electrically connected to a multiplicity of contacts. A protective encapsulant covers the die and a portion of the capacitor structure while leaving a surface of the second capacitor plate at least partially exposed. In some embodiments, one of the capacitor plates (typically the lower capacitor plate) is formed from the same lead frame sheet as the contacts. In LLP implementations, the lower capacitor plate is substantially co-planar with the contacts. Depending on the implementation the capacitor structure can be electrical connected in a variety of different manners. One or both of the plates can be electrically connected to either (or both of) selected bond pads on the die or selected leads or contacts.

Abstract: A pin grid array package comprises a number of signal pins and ground pins. At least one of the signal pins is a controlled impedance signal pin, i.e. a signal pin whose impedance is adjusted and/or reduced according to the present invention. The pin grid array package also includes a number of ground planes and signal planes. A controlled impedance signal pin is coupled to one of the signal planes by means of a signal via. A number of ground pins surround the controlled impedance signal pin. By varying the arrangement, number, and separation distance between the ground pins and the controlled impedance signal pin, the impedance of the signal pin is adjusted and/or reduced. Depending on the particular circuit or logic function assigned to a signal pin and its adjacent signal pin, a different degree of impedance control and/or reduction can be achieved by the present invention.

Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node.

Abstract: A filter layer and a buffer layer are sequentially laminated on a first principal face of a semiconductor substrate, and an island-shaped light absorption layer and a window layer are laminated on top of the buffer layer. A diffusion region in which p-type impurities have been diffused is formed in the window layer. An n-side electrode and a p-side electrode are formed on the buffer layer and the diffusion region, respectively. A light incidence portion is formed on the buffer layer where the light absorption layer has not been formed.

Abstract: An apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board are provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.

Abstract: Provided is a bonding pad structure of a semiconductor device that is unlikely to give rise to an open failure caused by the electromigration in the pad wiring portion. The input-output signal current and the power supply current of the semiconductor chip flowing through the bonding wire is branched to flow from the bonding region into the underlying metal wiring through via metals. A via metal connecting region consisting of the underlying metal wiring layer is formed in the lower peripheral region of the bonding region so as to allow the current flowing from the bonding wire to be branched from the upper via metal connecting region formed in the bonding pad region into the underlying metal wiring connected to the underlying via metal connecting region through a plurality of via metals so as to moderate the current concentration and, thus, to avoid the open failure caused by the electromigration.

Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

Abstract: A gate electrode is in Schottky contact with the surface of a semiconductor substrate and extends in a first direction. A drain electrode is disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and is in ohmic contact with the semiconductor substrate. A source electrode is constituted of a main part, an overhanging part and a shielding part. The main part is in ohmic contact with the semiconductor substrate in the region across the gate electrode from the drain electrode. The shielding part is disposed between the gate electrode and the drain electrode and extends in the first direction. The overhanging part passes over the gate electrode and connects the shielding part with main part. The size of the overhanging part along the first direction is smaller than the side of the shielding part.

Abstract: A light emitting diode assembly with low thermal resistance comprises an LED, a circuit board and a heat-dissipating substrate. The LED has a die mounted on a heat-dissipating plate and pads connected to a printed circuit board. The LED is mounted on a circuit board and a heat-dissipating substrate, whereby the thermal resistance of the LED assembly can be advantageously reduced to enhance the performance of the LED assembly.

Abstract: In a flat-type semiconductor stack formed by alternately stacking flat-type semiconductor devices (1) and heat-radiating elements (2), a projecting pin (7) is provided on a contact surface of at least one flat-type semiconductor device (1) while a positioning recess (8a) and a guide groove (8) are formed in a contact surface of at least one heat-radiating element (2), the guide groove (8) extending directly from the positioning recess (8a) to a side surface of the heat-radiating element (2). The flat-type semiconductor device (1) is aligned with the heat-radiating element (2) by fitting the pin (7) in the guide groove (8) and sliding the pin (7) along the guide groove (8) until the pin (7) stops to slide at the positioning recess (8a).