Abstract: A micromechanical device having a substrate wafer, a functional layer situated above it which has a mobile micromechanical structure, and a cap situated on top thereof, having a first cavity, which is formed at least by the substrate wafer and the cap and which includes the micromechanical structure. The micromechanical device has a fixed part and a mobile part, which are movably connected to each other with at least one spring element, and the first cavity is situated in the mobile part. Also described is a method for producing the micromechanical device.

Abstract: There is provided a solid-state imaging device including a semiconductor base element, an organic photoelectric conversion layer formed above the semiconductor base element, a contact hole formed in an insulating layer on the semiconductor base element, a conductive layer formed in the contact hole and electrically connecting a photoelectric conversion part which includes the organic photoelectric conversion layer with the semiconductor base element, and a contact portion which is formed by self-alignment with the conductive layer in the contact hole in the semiconductor base element, and connected to the conductive layer.

Abstract: In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm2/Vs or more.

Abstract: A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.

Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

Abstract: A method for manufacturing a display substrate includes a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode includes: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.

Abstract: An organic light emitting diode display includes a plurality of first signal lines, a first insulating layer covering the first signal lines, a plurality of second signal lines on the first insulating layer and crossing the first signal lines, and a plurality of pixels connected to the first signal lines and the second signal lines. A groove in the first insulating layer is between adjacent ones of the pixels and a filling material in the groove.

Abstract: A method of forming an active matrix pixel that includes forming a driver device including contact regions deposited using a low temperature deposition process on a first portion of an insulating substrate. An electrode of an organic light emitting diode is formed on a second portion of the insulating substrate. The electrode is in electrical communication to receive an output from the driver device. At least one passivation layer is formed over the driver device. A switching device comprising at least one amorphous semiconductor layer is formed on the at least one passivation layer over the driver device.

Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.

Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by an inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode is disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.

Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.

Abstract: The present application discloses an array substrate. The array substrate includes a liquid crystal capacitor; and a storage capacitor having a first electrode, a second electrode, and an electrolyte layer sandwiched by the first electrode and the second electrode. The storage capacitor is an electrochemical capacitor coupled in parallel with the liquid crystal capacitor.

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material. The precursor magnetic material included a diffusible species and at least one other species. An oxide region is disposed between the magnetic region and another magnetic region, and an amorphous region is proximate to the magnetic region. The amorphous region includes an attracter material that has a chemical affinity for the diffusible species that is higher than a chemical affinity of the at least one other species for the diffusible species. Thus, the diffusible species is transferred from the precursor magnetic material to the attracter material, forming a depleted magnetic material. The removal of the diffusible species and the amorphous nature of the region of the attracter material promotes crystallization of the depleted magnetic material, which enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.

Abstract: A method for fabricating a semiconductor device having a uniform spacer thickness between field-effect transistors (FETs) associated with regions of the device is provided. A first semiconductor material is epitaxially grown in a first source/drain region within a first region of the device associated with a first FET. A capping layer is selectively formed on the first semiconductor material by forming a layer over the first and second regions that reacts with the first semiconductor material to form the capping layer. A second semiconductor material is epitaxially grown in a second source/drain region within a second region of the device associated with a second FET. The capping layer caps the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material to provide the uniform spacer thickness between the first and second FETs.