Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film.

Abstract: An array substrate and a manufacturing method thereof, and a display device. The array substrate includes: a base substrate, including a first surface and a second surface opposite to each other, and a through-hole penetrating the base substrate from the first surface to the second surface; a data line on the first surface of the base substrate, the data line being at least partially filled in the through-hole; a thin film transistor on the second surface of the base substrate, the thin film transistor including a source electrode and a drain electrode, and the source electrode being electrically connected to the data line.

Abstract: The disclosure relates to a semiconductor component having an SiC semiconductor body and a first load terminal on a first surface of the SiC semiconductor body. A second load terminal is formed on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component has a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor area of a second conductivity type which is electrically connected to the first load terminal. A pn junction between the drift zone and the first semiconductor area defines a voltage blocking strength of the semiconductor component.

Abstract: A display substrate, a manufacturing method thereof and a display device. The display substrate includes a working area and a sealant setting area outside of the working area. The display substrate further includes: a base substrate, a first conductive structure on a first side of the base substrate, and a second conductive structure on one side of the first conductive structure away from the base substrate. The first conductive structure and the second conductive structure are in the sealant setting area. The second conductive structure at least includes an inclined part inclined relative to a main surface of the base substrate. The inclined part is configured to allow at least part of light to be exited out directly over the first conductive structure after the light incident into the inclined part from a second side of the base substrate opposite to the first side is reflected by the inclined part.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

Abstract: The present inventive concept relates to a thermal radiation body for cooling a heating element, which includes a pattern unit including a pore part provided as an empty space or filled with a gas phase and a cover part covering the pore part and dissipates heat of the heating element through heat radiation.

Abstract: This electromagnetic wave detector that detects electromagnetic waves by performing photoelectric conversion includes: a substrate; an insulating layer that is provided on the substrate; a graphene layer that is provided on the insulating layer; a pair of electrodes, which are provided on the insulating layer, and which are connected to both ends of the graphene layer, respectively; and a contact layer that is provided such that the contact layer is in contact with the graphene layer. The contact layer is formed of a material having a polar group, and a charge is formed in the graphene layer by having the contact layer in contact with the graphene layer.

Abstract: A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.

Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.

Abstract: A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.

Abstract: An image sensor includes a semiconductor substrate having opposite first and second surfaces, a wiring structure on the first surface of the semiconductor substrate, and a refractive structure on the second surface of the semiconductor substrate. The refractive structure includes a first anti-reflective layer on the second surface of the semiconductor substrate, a refractive pattern on the first anti-reflective layer, an insulation layer on the first anti-reflective layer, and a second anti-reflective layer on the refractive pattern and the insulation layer. The refractive pattern includes first refractive parts spaced apart from each other in a first direction parallel to the second surface of the semiconductor substrate, and the insulation layer fills spaces between the first refractive parts.

Abstract: A semiconductor element package includes: a semiconductor element arranged above a first substrate; first and second electrodes arranged above the first substrate and electrically connected to the semiconductor element; a housing which is arranged above the first substrate and arranged around the semiconductor element, and which has a stepped portion in the upper area thereof; a diffusion part arranged on the stepped portion of the housing and arranged above the semiconductor element; and a plurality of via holes penetrating the first substrate and the housing.

Abstract: A method of fabricating a multi-color display includes dispensing a photo-curable fluid over a display having an array of LEDs disposed below a cover layer. The cover has an outer surface with a plurality of recesses, and the photo-curable fluid fills the recesses. The photo-curable fluid includes a color conversion agent. A plurality of LEDs in the array are activated to illuminate and cure the photo-curable fluid to form a color conversion layer in the recesses over the activated LEDs. This layer will convert light from these LEDs to light of a first color. An uncured remainder of the photo-curable fluid is removed. Then the process is repeated with a different photo-curable fluid having a different color conversion agent and a different plurality of LEDs. This forms a second color conversion layer in different plurality of recesses to convert light from these LEDs to light of a second color.

Abstract: A variable resistance memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction, the second direction intersecting the first direction on the first conductive line, a fixed resistance layer between the first conductive line and the second conductive line, and a variable resistance layer between the first conductive line and the second conductive line, wherein the fixed resistance layer and the variable resistance layer are electrically connected in parallel to each other between the first conductive line and the second conductive line.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

Abstract: Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC.

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.