Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.

Abstract: A thin-film transistor substrate includes a thin-film transistor and a light-shielding part. The thin-film transistor includes a gate electrode, a semiconductor part made from a semiconductor material and superimposed on a part of the gate electrode via a first insulating film, a source electrode on a part of the semiconductor part and connected to the semiconductor part, and a drain electrode on a part of the semiconductor part and connected to the semiconductor part with spaced apart from the source electrode. The light-shielding part includes a first light-shielding section disposed above the semiconductor part, the source electrode, and the drain electrode via the second insulating film and superimposed on the semiconductor part, and a second light-shielding section not to be superimposed on the gate electrode, the source electrode, and the drain electrode and having an opening adjacent to the thin-film transistor.

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate; wherein the base substrate is provided with at least one thin film transistor, each of the at least one thin film transistor includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; and wherein, at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode.

Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.

Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

Abstract: A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Abstract: A light emitting device (LED) package includes: a substrate having a loading surface, a mounting surface and a pair of concave portions formed at both ends of the substrate, wherein each of the concave portions has an inner surface intersecting both of the loading surface and the mounting surface; metal wirings including a pair of electrodes, which covers a portion of the loading surface and the mounting surface and the inner surface, and a conductive part disposed on the loading surface; an LED chip loaded on the conductive part; a housing having a side wall surrounding the LED chip and a supporting surface facing the loading surface; and a covering member which is disposed on the loading surface and has a closing portion overlapping at least a portion of the concave portions when viewed from above, wherein at least a portion of the supporting surface is fixed to the closing portion.

Abstract: An organic electroluminescence device includes a first electrode, a hole transport region on the first electrode, a light emitting layer on the hole transport region, an electron transport region on the light emitting layer, and a second electrode on the electron transport region. The electron transport region includes an electron transport layer directly on the light emitting layer. The electron transport layer includes a first ternary compound including a halogen element.

Abstract: An electroluminescence display device is disclosed, which may use a polysilicon thin film transistor and an oxide thin film transistor together by using a dual line with respect to a plurality of switching transistors arranged on the same line. The electroluminescence display device includes a first active layer; a first gate line arranged on the first active layer and intersecting the first active layer; a second active layer forming a channel different from that of the first active layer, arranged on the first gate line; and a second gate line arranged on the second active layer and intersecting the second active layer. The first gate line and the second gate line are overlapped with each other, and the first gate line and the second gate line supply the same gate signal.

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a first lower area provided on the semiconductor substrate, and including a plurality of magnetoresistive effect elements, a second lower area provided on the semiconductor substrate, and being adjacent to the first lower area, a first upper area provided above the first lower area, and including a first material film formed of an insulating material or a semiconductor material, and a second upper area provided above the second lower area, being adjacent to the first upper area, and including a second material film formed of an insulating material different from a material of the first material film.

Abstract: A display device includes a flexible substrate, a plurality of thin film transistors (TFTs), a first electrode arranged between a channel of one of the plurality of TFTs and the flexible substrate, at least one inorganic insulating film arranged between one of the plurality of TFTs and the first electrode, a second electrode arranged on the opposite side to the side where one of the plurality of TFTs is arranged with respect to the first electrode, and an organic insulating film arranged between the first electrode and the second electrode.

Abstract: An ultraviolet light-emitting element includes: a multilayer stack in which an n-type AlGaN layer, a light-emitting layer, a first p-type AlGaN layer, and a second p-type AlGaN layer are arranged in this order; a negative electrode; and a positive electrode. The first p-type AlGaN layer has a larger Al composition ratio than first AlGaN layers serving as well layers. The second p-type AlGaN layer has a larger Al composition ratio than the first AlGaN layers. The first p-type AlGaN layer and the second p-type AlGaN layer both contain Mg. The second p-type AlGaN layer has a higher maximum Mg concentration than the first p-type AlGaN layer. The second p-type AlGaN layer includes a region where an Mg concentration increases in a thickness direction thereof as a distance from the first p-type AlGaN layer increases in the thickness direction.

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.