Abstract: A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

Abstract: A flexible circuit board, a display device and a method for mounting a flexible circuit board are disclosed. The flexible circuit board includes: a bendable portion, the flexible circuit board being bendable at the bendable portion to go into a bent state so as to be connected to a workpiece; and at least one opening in the bendable portion. In response to the bent state, a gap is formed between the bendable portion and the workpiece, and the at least one opening is in communication with the gap.

Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: A display panel includes a substrate, a thin film transistor (TFT) layer on the substrate, and multiple connection lines disposed between the substrate and the TFT layer. The TFT layer includes TFTs and signal lines connected to the TFTs for providing signals to the TFTs. Each connection line is electrically connected to a signal line. The present invention also teaches a display panel manufacturing method. The present invention has the connection lines formed in the display area, instead of in the non-display area, thereby reducing the width of the non-display area.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate and a first crack-detecting structure positioned in the substrate and comprising a first capacitor unit. The first capacitor unit comprises a first bottom conductive layer positioned in the substrate, a first capacitor insulating layer surrounding the first bottom conductive layer, and a first buried plate surrounding the first capacitor insulating layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: The present technology relates to a photoelectric conversion element, a measuring method of the same, a solid-state imaging device, an electronic device, and a solar cell capable of further improving a quantum efficiency in a photoelectric conversion element using a photoelectric conversion layer including an organic semiconductor material. The photoelectric conversion element includes two electrodes forming a positive electrode (11) and a negative electrode (14), at least one charge blocking layer (13, 15) arranged between the two electrodes, and a photoelectric conversion layer (12) arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer (13) or a hole blocking layer (15), and a potential of the charge blocking layer is bent. The present technology is applied to, for example, a solid-state imaging device, a solar cell, and the like having a photoelectric conversion element.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate including a front surface, a back surface opposite to the front surface, and a light-sensing region extending from the front surface into the semiconductor substrate. The image sensor device includes a light-blocking structure in the semiconductor substrate and surrounding the light-sensing region. The light-blocking structure includes a conductive light reflection structure and a light absorption structure, and the light absorption structure is between the conductive light reflection structure and the back surface. The image sensor device includes an insulating layer between the light-blocking structure and the semiconductor substrate.

Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.

Abstract: This disclosure describes optoelectronic modules, methods for manufacturing pluralities of discrete optoelectronic modules, and optoelectronic molding tools. The methods include coating a substrate wafer and a plurality of optoelectronic components with a photosensitive material, and further include exposing select portions of the photosensitive material to electromagnetic radiation. The exposed portions delineate at least in part the dimensions of the optical channels, wherein the optical channels are associated with at least one optoelectronic component. In some instances, optical elements are incorporated into the optical channels. In some instances, the exposed portions are the optical channels. In some instances, the exposed portions are spacers between the optical channels.

Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.

Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.

Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.

Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.

Abstract: The invention provides an array substrate and manufacturing method thereof.

Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.

Abstract: Disclosed are a display panel and a display device, and the display panel includes a display area and a non-display area adjacent to the display area, the display area includes a first display area and a second display area, and the number of pixels in each column of pixels in the first display area is less than that of pixels in any column of pixels in the second display area.