Abstract: A mapping-type data signal optimizer performs a DEVICE-SPECIFIC ATTRIBUTE ELIMINATION routine. If field attributes in an outgoing signal do not affect the appearance of a data display on, or the operational characteristics of, a peripheral device receiving the outgoing signal (e.g., field attributes are essentially meaningless on printers), then the outgoing signal is reformed so as not to include those attributes.

Abstract: In a data communication management system, a first transaction causes an application program to start. When a transaction arises, it is determined whether the transaction is to be batch processed as one of a plurality of transactions. Batch processing is determined based on the name of the transaction and the name of a application program requested. If it is determined that the transaction should not be batch processed, the transaction undergoes ordinary processing. If it is determined that the transaction is to be batch processed, the transaction is stored in a batch process queue. The application program for all transactions stored in the batch process queue is started when the number of transactions stored in the queue has exceeded a certain number or when a predetermined time length has elapsed after any transaction has been stored in the queue. After the application program is terminated, a batch synchronous point process is carried out for all the transactions.

Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus.

Abstract: A data processing system comprises a number of processing nodes, each having a processor and a local store. The workload of the system is represented by packets, including function packets specifying a function and pointers to one or more argument packets to which the function is to be applied.The argument packets include stateholder packets, which represent variable values, such as semaphores real time clocks and so on. When a node processes a function packet, it checks whether any of its arguments is a stateholder resident in a different processing node. If so, the function packet is exported to the node in which the stateholder resides. This avoids the need for making copies of stateholder packets, and hence avoids any problems of copy consistency. Each function packet is allowed no more than one stateholder as a strict argument.

Abstract: In a file management system a plurality of information processing devices are provided with files of tree structure. The information processing devices are linked through a communication line and dispersed files are utilized by a plurality of users in common. Each of the users can construct his own file without having any influence on the others. A table is provided including a column indicating the relation of links for the case where an arbitrary branch of a tree structure, included within at least one information processing device, is linked with a part of files included within another information device and a column specifying groups, for which the relation of links is valid. Linking is only permitted for access demands from members belonging to the group for which the relation of links is indicated as valid, to the part of the files of the other information processing device.

Abstract: A Digital Service (DS) interface interfaces a Personal Computer (PC) to the DS directly at the PC's data bus. The DS interface has independent transmit and receive memories for transmitting and receiving the digital data at high speeds. FIFO memories buffer data between the PC's data bus and the DS interface prior to being converted to bipolar digital signals before transmission and after being received and converted to amplitude discrete digital signals from bipolar digital signals.

Abstract: A system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory.

Abstract: Apparatus and method for performing optimized execution of a prior and a subsequent operations having common process steps. Each operation is partitioned into at least one process step, and the steps of each operation are assigned a path number. Execution of the process steps of each operation is controlled by a set of flags associated with the given operation. Upon invocation of two operations, the path numbers of the two operations are compared, to determine commonality of process steps between the operations. If common process steps exist, the flags of the subsequent operation corresponding to the common process steps are cleared, to prevent execution of the common process steps during the later execution of the subsequent operation. Upon completion of the common process steps during execution of the prior operation, an intermediate result is transferred to a storage associated with the subsequent operation, and the prior operation continues to completion.

Abstract: An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area boundary, a page table is prepared for each virtual address space. Thus, virtual pages which are not used as the system common area in the bondary segment can be used by jobs as job private areas.The real page is fixedly allocated to the virtual page belonging to the system common area in the boundary segment. Thus, it is not necessary to simultaneously update page tables for the system common area. Those virtual pages may be subjects of dynamic allocation of the virtual storage.

Abstract: A method of operating a computer system to store and retrieve information in a database uses a signature file of the database that is divided into subsets. A word signature is mapped to a particular subset during creation of the file and the same mapping information is used to retrieve the information in response to a query word. Each word signature is a logical word signature and has two components a physical word signature and a subset designation field. In this way, when information is retrieved from the database, only that subset containing the relevant word signature is scanned. The signature file is automatically created by the system as the database is stored on the data storage modules.

Abstract: In a computer system of a microprogram control type which processes a succession of instructions to produce a succession of store data units and a succession of store requests under control by a microprogram controller, the store data units being written into a memory by control of a memory controller according to the store requests, a specific one of the instructions being retried from a checkpoint on occurrence of an error during current processing of the specific instruction, the microprogram controller controls execution of a state transition which results in cancellation of the checkpoint on occurrence of the state transition during processing the specific instruction.

Abstract: A computer comprises an instruction memory storing therein instruction codes and including a plurality of divided address spaces, and a CPU receiving an instruction read out of the instruction memory for executing the read-out instruction and outputting an address data for an instruction code to be next executed to the instruction memory. In addition, there is provided a space code memory storing respective codes indicative of the divided address spaces within the instruction memory for respective instruction codes stored in the instruction memory, for generating an address space code for an instruction to be executed next to an instruction code designated by the address given to the instruction memory.

Abstract: A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

Abstract: A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not guaranteed to be independent of data information used in the first sequence. Increased data handling capacity is achieved in the following manner: both sequences are initially executed in parallel. An address included in a read instruction associated with the second sequence is intermediately stored in an auxiliary memory if it has not been previously selected in conjunction with a write instruction of the second sequence. The intermediately stored address is compared with the write addresses of the first sequence and execution of the second sequence is restarted upon detection of a match.

Abstract: An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communications paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path.

Abstract: A programmable element (PE) for implementing programmable logic circuits includes a run address register, a load address register and a random access memory (RAM). The RAM is initialized with a state transition table using the load address register. After RAM initialization, and at each clock transition, the run address register is loaded with external inputs and a present state. The present state is received as the next state output of the RAM from internal feedback lines from the RAM output to the run address register inputs. The RAM output is divided into a next state which is stored in the internal feedback lines and element data outputs to an destination external to the programmable element. A state processor (SP) for implementing complex programmable logic circuits includes a plurality of programmable elements and a matrix switch. The matrix switch provides external feedback for programmable elements. In addition, any programmable output may be routed to any programmable element input.

Abstract: A programmable controller according to the present invention has memory means (P) for registering any functional instruction. On the basis of a functional instruction stored in the memory means, an individual functional instruction (Func) is repeatedly output to a machine tool. When the format of a functional instruction changes due to a difference in input conditions, input condition (B, C) data are created as a ladder and, by executing a single fixed input condition (A), the lead address of an area storing the parameter of the individual functional instruction is called and output, whereby a functional instruction of a unified format is executed.

Abstract: This invention relates to assigning disk drives associated with both a host computer and a remote computer coupled together by a communication link using normal DOS driver letters. DOS initialization of the host computer is postponed until a remote session is established with the remote computer and the remote computer provides information regarding the disk drives associated therewith. Upon receiving the disk drive information from the remote computer, the host completes its initialization and assigns drive letters associated with diskette drives associated with the host computer to diskette drives associated with the remote computer. Thus, host diskette drives are logically replaced by remote diskette drives. Any hard disk drives associated with the remote computer are assigned the next available drive letter on the host computer.

Abstract: A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

Abstract: An address translation buffer control system includes multiple prioritized address translation buffers and circuitry for changing the contents of the buffers. When a desired address translation pair is not present in the buffer having the highest priority, the contents of the highest priority buffer are replaced with contents from a lower priority buffer. If a desired address translation pair is not present in any buffer, the contents of the lowest priority buffer are replaced.