Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements.

Abstract: A vector computer includes memory 11 for storing vector data, and arithmetic unit 12 for sequentially reading out the vector data from memory 11, performing vector processing based on a pipeline system, and storing an operation result in memory 11. The vector computer further includes read/write controller 13 for storing white addresses of the memory at which results of operations being performed in stages of a pipeline are to be written, comparing the write addresses with a read address generated by arithmetic unit 12, and when at least one of the write addresses coincides with the read address, detecting that data designated by the read address is being operated in any stage of the pipeline, i.e., is not determined yet, thereby inhibiting reading of the data designated by the read address from memory 11.

Abstract: Two access buses are arranged such that one access bus connects a memory section from which data is retrieved to a retrieval section, and the other access bus is connected to a control section. The two access buses are connected to each other through a gate. While the retrieval section is operated, the gate is disabled. Otherwise, the gate is enabled. Key words located at different positions are sampled, and compared with a plurality of key words externally supplied. A data string to be retrieved is then recognized in accordance with a combination of a plurality of comparison results. In addition, retrieval is performed upon determination whether data string length data added to the start portion of the data string or predetermined data string length data supplied from the control section is used as data string length data for generating the start address of the next data string.

Abstract: Interface circuitry (24) is provided which automatically detects which of two types of microprocessor is connected to the interface and configures the interface accordingly. A "type" flip-flop (36, 38) is initially set to expect a first type of microprocessor (10) and the interface is configured to expect a read and a write strobe. When a write cycle is performed by a second type (14) of microprocessor, the "type" flip-flop changes state and reconfigures the interface to expect a data strobe and a read/write indicator signal.

Abstract: A data name standardizing/unifying system for standardizing the names of data belonging to data items having different names and transferred or compared among data files so as to be unified for programs. For standardizing the data names, names of data items assumed to have same contents are gathered and a table indicating data names to be replaced are generated to be displayed together with prompting for entry of the standard data name to replace. From this table, standardization for data names is accomplished by this replacement of the data name in the programs. For identifying the standardized data names created for the different files, different file names or different and upper file names are added to a division of program which refers to the files.

Abstract: A digital signal processor for determining the maximum and minimum values of a plurality of data items wherein operations of an arithmetic logic unit and data memories are controlled by micro-instructions, including a device for decoding specified bits of an operand of the micro-instruction, a device for detecting a value of a condition code which has been designated by an output of the decoding device, and a control device for executing a logical operation between the output of the detection device, which becomes "1" if the value of the condition code is true, and a decoded value of an operation code of the micro-instruction and to generate a control signal for the arithmetic logic unit on the basis of a result of the logical operation.

Abstract: A bit density controller is capable of transmitting no more than 15 consecutive 0-bits to be sent serially in a data bit sequence, without a 1-bit, for operating on the AT&T T1 network. The bit density controller includes a state machine having a state index and a substitution device coupled to the state machine. The bit density controller additionally can include a buffer for storing at least one frame of the data bit sequence, a memory for storing overhead bits, and an overhead bit inserter for inserting overhead bits into the data bit sequence.

Abstract: A bus data path control scheme facilitates communications in a data processing system between subsystem elements that have different data widths. A plurality of buses is provided whereby each subsystem or element is connected to one of the plurality of buses. A control logic array detects requests to transfer data between subsystems. Each of the plurality of buses are connected to one another through a bidirectional transceiver. Once the control logic array detects the request for transferring data between subsystems, the array and the transceiver operate in concert to permit subsystem devices having different data widths to communicate with one another. In particular, the array and transceiver act to redirect data so that as it is shifted from a first bus to which the sending subsystem is connected to a second bus to which the receiving subsystem is connected, the data is moved into the proper bit location on the second bus so as to be received properly by the receiving subsystem.

Abstract: The construction and display of operator messages representative of alert conditions in a network is described. Code points, which are strings of bits, are generated in response to an event in a device attached to the network. The code points are used to index predefined tables that contain relatively short units of text messages in operator selectable languages to be used in building an operator's information display. A product attached to a network, an alert sender, will generate a series of code points representative of desired display messages for an operator. The messages are indepedent of the specific alert sending product insofar as an alert receiver is concerned. The operator can also choose between detailed and general display messages. The code points are hierarchically arranged so that if the alert receiver does not have the most up to date set of messages, the alert receiver will display a more generic message which is still representative of the event.

Abstract: A printer controller is provided for operatively connecting a printer to any one of a plurality of information processing equipments each having a protocol different from that of the printer. The printer controller includes a microprocessor which reads printer control informations provided by each information processing equipment, based on the specific protocol of the information processing equipment, converts the control informations into printer functional parameters corresponding to printer control commands specified by the control informations, and controls the printer directly in accordance with the printer functional parameters.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

Abstract: A data bus system for vehicles in which the various subsystems communicate with one another via a common data bus is provided in which the subsystems are in each case connected with the data bus via a station. The stations have registers for the storage of data required and furnished by the corresponding connected user. These stations, for the reception of the data required by the corresponding subsystem, are continuously connected to the data bus, while the stations for the sequential transmitting of the data furnished by the corresponding subsystem are sequentially connected to the data bus for a time interval equaling the length of the data to be transmitted.

Abstract: An information processing apparatus is provided with an optical disk for storing image data and code data. The code data stored in the optical disk have different data format. The optical disk further stores a flag indicating the data format of each code data. When retrieving the code data from optical disk, the processing apparatus processes the retrieved code data according to the data format indicated by the flag, and stores the processed data into a floppy disk.

Abstract: A data processing system in which any one of a plurality of different or similar interface circuit cards can be located into any one of a number of slots of the data processing system without preassignment. The system includes a master processor which communicates with the interface cards through a data bus, address bus and control bus. Each interface card includes decoding means which computes during an initialization sequence a random address which will be used to decode the address bus after the initialization sequence. Once the different cards have their specific addresses, the system can reassign a new address according to the identifier register and the nature of the card thereby allowing the application programs to address each card separately and irrespective of the prior random address. This system may be used in small computers like the personal computer which are not designed with any slot identifier device.

Abstract: Provision is made for conducting an I/O channel diagnostic test by using a first I/O channel in a test mode to provide a sequence of test signals to a second I/O channel. The second I/O channel responds to the test sequence by producing a series of data transfer protocol signals which are conducted to the first channel. In the first channel, the series of data transfer protocol signals are used to check operation of the second channel.

Abstract: This device is an add-on accessory for existing personal computer systems. This device is a user definable, keyboard MACRO storage device which operates independently of the hardware and software installed in the computer, plugs into the keyboard line of the computer and stores a plurality of different keyboard MACROs, that is, keyboard keystroke sequences. internally, the device contains a dedicated microprocessor which monitors and controls all operations. It stores the MACROs, selected by the user, in its non-volatile memory and associates them with user-defined commands. The commands are then subsequently executed via the device's keypad. The invention may be installed permanently in the keyboard line without taking any precautions to save the MACROs when the computer is powered down or, in the alternative, when the device is removed from the keyboard line. The device performs detailed internal self checks in order to insure its correct operation.

Abstract: Microprocessor controlled apparatus for interconnecting at least two very high speed integrated circuit chips having digital inputs and outputs. Included are a local data bus, a microprocessor unit and its associated memory unit, and a plurality of functional interface units. One functional interface unit is connected between the microprocessor and the local bus. The remaining functional interface units are connected between the local bus and one of the integrated circuit chips so that all of the functional interface units are responsive to control commands from the processor and pass data from one integrated circuit chip to another. The circuit chips can be custom or can be customized via substrate interconnection.

Abstract: The computer hardware executive is a special purpose associative processor hich interfaces to the memory bus of a digital computer to provide high-speed execution of executive functions. These functions include task registration, task synchronization, normal, time-dependent and time-critical event registration and triggering, hierarchical event-to-semaphore translation, and buffer allocation. The programmer invokes an executive function by accessing the address in the hose computer address space dedicated to that function. The data written to or read from that address is the function operated or result, respectively. The hardware executive maintains task and event tables internally within its associative memory. The memory is organized such that the same field bit position of all table entries is accessed in parallel within a microinstruction cycle. Searches are performed by sequencing through the bit positions of interest.

Abstract: There is described an emergency action system which is an integrated security control and communications system employed for relatively large and secure installations such as embassies, military buildings and so on. The emergency action system apparatus consists of two major subdivisions. A first subdivision is a security and control subsystem which operates to monitor and control sensors and actuators associated with an intrusion detection system. The security and control subsystem handles event logging, generates alarm map displays and switches and distributes surveillance video. The second subdivision of the system is associated with user emergency action consoles which consoles provide the interface and handle voice and data communications to enable the user to interface with the existing communications system as located on the installation as well as with the intrusion detection system.

Abstract: An interface between a computer and an asynchronous communications line in which asynchronous data on the communications line sets a register made up of latches designed according to LSSD rules, which is then read out and reset in synchronism with the computer. The latches for each individual bit position of the register are edge triggered providing for maximum speed of transmission and are designed to be tested using LSSD test criteria. Data is frozen in the register upon receipt of a data valid signal. The contents of the register are then synchronously gated internally within the computer.