Abstract: A page-accessing method in a segmented tablespace 10 which eliminates unnecessary reading and locking. The tablespace comprises data pages 18 grouped into identically-sized segments 16, each segment storing data for a single table. A status indicator 26 for each data page of a segment is kept in a separate segment control block 20 stored on a space map page 14. Five data page status indicator values are maintained:(1) FULL (26a) - entirely full of current data;(2) PARTIALLY FULL (26b) - partially full of current data;(3) UNFORMATTED (26c) - empty; contains no data;(4) MASS DELETE (26d) - contains only obsolete data because of an unqualified deletion (mass delete) of data; or(5) QUALIFIED DELETE (26e) - contains only obsolete data because of a qualified deletion of data.When scanning over the data in a segment, UNFORMATTED and MASS DELETE pages are skipped. QUALIFIED DELETE pages are locked, and then skipped if they still contain only obsolete data when the lock is obtained.

Abstract: A compiler generates compiled object code from source code of a computer program in a manner that produces efficient object code for a computer with dissimilar register spaces.

Abstract: A document processing system including a document structure and a library of routines for manipulating the document structure. The components of the document structure are made up of individually-locatable blocks. The components include a chain of text blocks which contains at least one document page and includes at least one block, one or more chains of reference blocks, each chain containing a reference and including at least one reference block, information attributes in the text blocks which relate locations in the text of the document to item numbers referring to references, a page index which relates page numbers to the text blocks at which the pages begin, and a reference index which relates each item number to the first reference block in the chain containing the reference. The document structure may only be manipulated by means of routines in the document manager library. The routines in the library are accessible to programs such as editor programs and printing programs which manipulate documents.

Abstract: A system for troubleshooting or debugging the various modules of a digital computer which are connected to the ports of a common system bus. A control unit transmits serial function and data codes to a serial bus link gate array whose parallel outputs are further processed to generate steering and clock commands. A first set of bus interface multiplexers are connected to each of the lines of the address, data and control fields of the system bus. A second set of multiplexers cause information represented by digital signals on selected ones of the lines in selected ones of the fields to be stored in a plurality of RAMs in response to the steering commands. A trigger logic is provided for selectively starting and stopping different clock signals in response to the clock commands.

Abstract: In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit.

Abstract: A method for more accurately estimating the time required to process a data base query using a selected index. A selected number of the most frequently occurring index key values (38) are collected during an index sequential scan. These most frequency occurring values are stored as percentage frequencies of occurrence in the data base system's catalog (42). Estimated access and processing times (NPAR, NPAS, NCPU) for a given query are calculated based on the stored frequencies where possible. Where the query's search criteria specify values other than the stored most frequently occurring values, those values are assumed to be uniformly distributed.

Abstract: According to the present invention, using a display terminal for conversation, a module structure diagram (schemata expressive of the connectional relations among respective program modules) is created, and a processing flow diagram (a kind of processing flow chart), an internal data definition diagram (schemata for specifying the formats etc. of data for use in processes) and an interface data definition diagram (schemata for specifying the formats etc. of arguments, common data between the modules, etc.) are created for each module, the created contents being stored in a memory. Further, the schematic information items of the module structure diagram, processing flow diagram, internal data definition diagram and interface data definition diagram are read out from the memory for each module and have stereotyped sentences and symbols added thereto, to generate the individual sentences of a source program. These sentences are edited according to the rules of a language, to complete the source program.

Abstract: In a data processing system that includes a central processing unit (CPU) which performs functions on data characters based upon a set of program instructions, the central processing unit being of a type that includes: (a) an arithmetic logic unit for performing the functions on the data characters; (b) a plurality of internal registers for storing data characters; (c) a data bus both for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU; and (d) an address bus for transmitting receiving addresses of referenced program instructions, and wherein the contents of one of the internal registers forms part of the address of the referenced program instruction available on the address bus.

Abstract: The invention generally relates to improvements in the process and storage of formatted voice, graphic and image data. A new editing process allows the same commands to be applied to a plurality of data files of varying resolution and formats. The technique employs an edit tracking file to retain the edit commands applied to a file of a first format. The edit commands are then executed against a file of a second format to perform the identical editing steps to the second file. This process avoids the inaccuracies associated with converting information to a common format while providing the benefits of supporting multiple formats of file information.

Abstract: The improved memory system can use various memories, such as CCDs and RAMs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Abstract: A computer system is disclosed in which individual executing process can be replaced with updated or corrected versions of themselves without interrupting or otherwise interfering with the operation of the computer system. In particular, embedded in the process itself is a command or function or subroutine call which operates to overlay the process code in memory with an updated version of itself, without losing or altering the relationships of the process to the other processes in the computer.As an example, in a UNIX system, the execute command can be used to perform the replication function. The replication process can be triggered by an inter-process signal, by the occurrance of an external condition, or by a triggering signal embedded in the normal data input to the process.

Abstract: A programmable logic control (PLC) device for executing a logical operation process of a sequence for program. The PLC device includes a PLC control unit (10) and a high speed input/output module (20) capable of executing a logical operation at a high speed in response to an external input signal and externally outputting a result of the logical operation, whereby an external signal to be processed at high speed can be processed without using a special processing unit.

Abstract: A data processing system having a first logical device capable of sending and receiving clocked electronic data and a second logical device connected to the first logical device, the second logical device also being capable of sending and receiving clocked electronic data. A controller is connected to the first and second logical devices for controlling data transfer therebetween. The controller includes a clock edge generator and gating logic connected thereto for allowing the first logical device to accept data and the second logical device to send data during a time interval of an odd number of clock edges.

Abstract: In a data bus system which links a plurality of users, user access to the bus is provided by an arbiter which responds to a plurality of user requests for bus access by employing an adjustable priority scheme for granting access. When a user has access to the bus, the arbiter updates user priority by assigning the lowest priority to the current user and upwardly adjusting the priorities of all currently-requesting users.

Abstract: A computer having a file management system is presented. The file management system includes a plurality of application programs, a plurality of data files, a plurality of class data structures and a plurality of object data structures. Each class data structure includes a reference to an application program within the plurality of application programs. Each object data structure includes a reference to a class data structure from the plurality of class data structure and a reference to at least one data file from the plurality of data files.The use of object data structures adds a layer between a user of the computer and data files. This allows for the computer to refer to an object data structure and associated access files using a tag which is inaccessible to the user. The user refers to an object based on the physical location of the object on the screen. The user may also give the object data structure a name, which is wholly unconnected to the value of the tag.

Abstract: A system uses variable ranges to support symbolic debugging of optimized code. A debug symbol table is constructed which includes descriptions of each user resource in source code. Additionally, a range table is constructed. The range table contains, for each user resource which is stored in numerous locations during execution of the code, a list of ranges and a description of where the user resource may be found during each range. If the user resource is stored as a constant during a particular range, the value of the constant may be stored in the range table. The description of each user resource in the debug symbol table includes a flag which indicates whether there is a list of ranges in the range table for a particular user resource. If there is, the description of the particular user resource will include a pointer to the list of ranges for that user resource.

Abstract: A timer system comprises a plurality of timer channels serviced by a single service processor. Each of the timer channels is capable of both input (capture) and output (match) functions. The microprogrammed service processor is responsible for configuring each of the channels for their intended uses and for responding to service requests generated by the channels in response to the occurrence of timer events. Features of the timer channels include the ability to continuously execute capture functions without generating service requests, the ability to execute a single capture function and service request and protect the captured value from being overwritten until the service request has been responded to and the ability to combine match and capture functions in such a way as to place a time-out window on the capture event.

Abstract: A nibble-mode DRAM solid state storage device is organized into a plurality of sections each including a plurality of groups, each including a plurality of ranks of DRAM memory chips. A pipeline data path is provided into and out of each group and nibble-mode access is facilitated by simultaneous pipelining of data into and out of the memory while memory reference operations are accomplished.

Abstract: In a data processing system having a plurality of remote terminals, possibly of several kinds, connected by a plurality of communications media, also possibly of several kinds, from which terminals users may run a plurality of application programs in the central processing unit (CPU) of the data processing system, the CPU is provided with a network terminal driver for regulating transmissions between the various application programs and the various types of terminals over the various types of communications media. Means are provided for specifying the characteristics of the various types of application programs, terminals, and communications media, and the network terminal drive is responsive to those means.

Abstract: A memory cartridge having a case and a printed circuit board housed in the case is connected, in use, to a data processing unit including a microprocessor and a picture processing unit. A memory cooperating with the data processing unit is installed on the printed circuit board, and an area of the memory is divided into a plurality of banks. A multi-memory controller installed on the printed circuit board includes a plurality of registers into which microprocessor generated data, representing bank switching conditions, are loaded. An address for switching the memory banks is output in response to the content of at least one of a plurality of registers. Thus, by changing the above-described data, the microprocessor can specify a specific bank at a specific time and utilize that bank.