Abstract: Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a port for reading and writing, and at least one staging register interposed between the vector memory port and the processor; the port and the register are each sufficiently wide to span more than one data element. As a result, on average fewer than one read or write operation per data element is required to access the vector memory via the port. Access to the vector memory port (i.e.

Abstract: A microcomputer comprises a microprocessor chip and a memory chip coupled to each other. The memory chip includes a memory for storing various processing data, a bus interface for designating an address information of the memory to be accessed for a data transfer, and an address latch for temporarily holding the address information from the bus interface and so as to supply the address information to the memory. Furthermore, there is provided an automatically updated data pointer whose initial value is set with the address information supplied from the bus interface. In case of individually designating an address for each item of data to be transferred, the address latch is used to supply the address information to the memory so that an address is given to the address latch by the bus interface for each data transfer of one unitary data.

Abstract: A method for processing a distributed application program in a SNA type network having a host processor executing a virtual machine type operating system and a relatively large plurality of terminals, in which a plurality of run ready virtual machines are established at the host and primed by pre-initializing each machine with the host resident portion of the application program under the control of a Virtual Machine Pool Manager that was previously created. Primed virtual machines are assigned to process requests from the terminals for LU 6.2 type conversation with the application program since the virtual machine is pre-initialized the request is immediately accepted for processing. At the end of the conversation the primed machine is returned to the pool of primed machines to await the processing another request. The Pool Manager is provided with a control strategy which determines the number of primed virtual machines that are in the pool during any period of time.

Abstract: A network consists of a programmable controller coupled to several sensors by an interface circuit. A common communication protocol is used to exchange messages containing commands and data between the devices coupled to the network. A protocol message packet has a header with fields for a task command, sensor identification, device status information and error codes. The header contains the same fields whether the message packet is for the interface circuit or one of the sensors connected to it. The headers for message packets going to and from the programmable controller and the interface circuit also have the same fields although the contents of the fields may vary depending upon the direction of the message packet. The message packet may also contain several data blocks each specifying a separate operation for the sensor to perform.

Abstract: A method of storing data on a peripheral rotating disk memory system, which is connected to one of a plurality of central processor units via a common bus including temporarily storing, in an intermediate memory system connected to the bus, original data packets which are to be stored in the disk memory system separating data block and commands of the original data packets received by the intermediate memory system from each other, creating composite data packets containing a new command and all data of a number of original data packets received by the intermediate memory system, writing the composite data packets via the bus on the rotating disk memory device, and purging the intermediate memory system after completing a write operation.

Abstract: A method is disclosed for enforcing referential constraints on a record-by-record basis, immediately before or after each record is manipulated and while the record is still accessed, significantly improving the system's performance. Each record is visited only once to do both the constraint checking and the manipulation (insert/update/delete). If the constraint checking fails, then the entire relational operation of which the record manipulation is a part is backed out. For insertions, each record is first inserted 30, and then constraints respective the record are enforced 32,34. For updates, the record is updated 48 after constraints respecting the record's primary key are enforced 40,42, and before constraints respecting its foreign key(s) are enforced 44,46. Deletions are performed 52 before the constraints on the deleted record are enforced 54,56. Cascade deleted 58 are handled recursively 60. The method correctly processes cyclic constraints and self-referencing rows without special handling.

Abstract: A device for detecting whether addresses used for accessing in a memory mapped I/O system are present in the I/O area or not is provided. The device includes a mask register for logically ANDing with an incoming address. The output of the ANDing process is exclusive-ORed with an I/O address register. When an operand fetch is made to an I/O area the fetch is suspended during execution of preceding instructions. When the instruction fetch unit seeks an I/O area address, or the address calculation unit seeks an I/O area address, or data is fetched across a boundary of the I/O area, an exception is activated.

Abstract: A plurality of memory blocks, which includes a plurality of memory areas, each having a page number. Each of the memory blocks has a set number. A page controlling register stores mapping information and a page number of the memory areas. A mapping register stores mapping information including set information that indicates the set number of a memory block in which data supplied from a CPU is stored. A memory controller accesses the memory section in accordance with the mapping information.

Abstract: Microcomputer architecture is provided that facilitates a fully integrated circuit computer on a single integrated circuit chip. The architecture includes use of an integrated circuit ROM for program storage, an integrated circuit RAM or scratch pad memory for alterable operand storage, and integrated circuit logic. Additional architectural features include serial data communication, pulse modulated communication, eight bit instruction bytes, sixteen bit operand words, and shared I/O channels.

Abstract: A communications system for industrial controllers includes interface controllers which implement a remote command capability. The remote command feature allows conventional communications commands to be saved at a responding interface controller in a remote command table and performed at a later time. A "SAVE" type remote command includes an ID field and an embedded command. The embedded command is stored in the remote command table at a location corresponding to the ID field. The ID field is used to access the embedded command in subsequent remote commands. A "PERFORM" type remote command contains a string of ID's, which indicates which saved commands are to be performed and the order in which to perform them. When a PERFORM command is received, the conventional command stored in the remote command table is recalled and transmitted onto a communications network.

Abstract: A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.

Abstract: An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 "Port 0" and "Port 2" registers are output and functionally "recreated". An internal emulation mode is generated in the 8031 wherein internal SFR latch contents are output to the port leads during one state and the port drivers are tri-stated to allow in-level reading of the levels of the port leads during another state. The emulator circuit generates a "Force Ports" pulse that causes the "recreated" port registers of the external circuitry to "force" external "logic" levels onto the 8031" Port 0 and Port 2 leads.

Abstract: A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.

Abstract: In a memory access system used for receiving a logical address and a memory request, translating the logical address into a real address, and accessing a memory by using the real address, a non-address-translation portion, which is not an object to be translated, in the logical address is transmitted in advance to the memory through an address signal line when the memory request associated with the logical address supplied to the memory is generated, and an address-translation portion, which is an object to be translated, in the logical address is transmitted to the memory through the address signal line upon completion of address translation of the address-translation portion.

Abstract: A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: In a staging method and system for an unrewritable storage medium such as an optical disk in which the updating or deletion of stored information is possible only by annotatively recording information concerning the updating or deletion, information stored in the medium before any alteration or charge including addition, updating and deletion is made to the medium is staged on a staging file while positions of the read or staged information are stored on a management file. Thereafter, the last end of the information staged on the staging file is detected by referring to the information positions stored on the management file. Then, information concerning the addition is additionally recorded at a location on the staging file after the previously staged information while information concerning the updating or deletion is used to update or delete the information on the staging file at a location indicated by the information concerning the updating or deletion.

Abstract: A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.

Abstract: In a file transfer control among a plurality of computer systems, a plurality of data sets to be transferred are stored in a transaction file by executing transfer and receiving processings by use of control records. A plurality of data sets are stored in the transaction file together with information identifying transfer destinations. A transfer file contains control records each having ID information, and in a transfer operation, when a data set is moved from the transaction file to the transfer file, a store status in the transfer file is stored in a control record having ID information identical to ID information assigned to the data set. In response to a transfer execute instruction containing ID information, the pertinent data set is read for transmission by use of the control record.

Abstract: A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU.

Abstract: A multiprocessor system includes a segmentable parallel bus for dividing the multiprocessor system into several independent groups of processors. Each group of processors can access its segment of the segmentable parallel bus to carry on processing within the group simultaneously and independently of processing occurring in another group of processors on another segment of the segmentable bus. The multiprocessor system of this invention further has the capability to reconfigure the segments and processors associated therewith in order to cope with a failed processor or bus segment.