Abstract: A packet switch receives data and processes it for assembly into packages. A bus allows communication between each of the data processing units of the switch and one or more storage units for storing the data packets. Arbitration for deciding which of the processing units will be granted access to the bus is performed by a system which selectively and alterably designates any of at least two different levels of priority of access to the bus for each of the processing units, and the relative percentages of time of access for the different priorty levels. The system assures greater access to the bus by those of the processing units having the higher level of priority. If communication is provided by two buses, the requests for access are alternated between them.

Abstract: A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.

Abstract: A bus adapter connecting a high-speed pended bus to a slower speed non-pended bus includes a first module functioning as a node of the pended bus and a second module functioning as a node of the non-pended bus. An interconnect bus extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Abstract: An IC memory card includes one or more memory devices for storing data, a memory latch for storing a start address set from outside of the card, a circuit for generating a signal representing the memory capacity of the card and for outputting the signal outside of the card, and a comparator for comparing the start address set in the memory latch with an address sent from an address bus and for making the data stored in the memory devices accessible from the outside of the card when upper bits of the two address are identical to each other. A computer system employing a plurality of such IC memory cards receives the memory capacities of the cards and assigns start addresses to the cards in sequence. Intervals between start addresses of cards adjacent in sequence are based on the memory capacities of the cards. Thus, a plurality of cards of varying memory capacities may make up a memory map having a continuous range of memory with no empty memory regions therein.

Abstract: In operating a computer system which has changeable operating characteristics and configurations, the operating characteristics and configuration of the computer is investigated at each initialization thereof. In response to the results of the investigation, a system control program is customized to the current operating characteristics and configurations so that it can provide control of the computer system.

Abstract: A data processor in accordance with the present invention can normally operate bit-string data while avoiding a breakage of the data even in the case where a read-out area of the bit string and a write-in area thereof are overlapped each other by providing an operation code of an instruction with an option designating the direction of bit processing.

Abstract: Network interface software for use in a network of computers includes software providing protocols for transmission of messages without high level software acknowledgments required. Negative acknowledgments are relied on to indicate the failure of complete message reception.

Abstract: In an online system having processors which execute a plurality of online jobs, a standby processor is provided along with a wait job which is executed by this processor and which has organization information of a logical sum of organization information items of the plurality of online jobs. When a failure has occurred as to any of the online jobs, only the organization information item of the failed online job within the organization information of the wait job is left valid. Thereafter, a process of the failed online job is switched to and executed by the wait job.

Abstract: A computer communication system including a comunication medium, a plurality of nodes coupled to the communication medium, and a transfer format selection means for selecting a format for the transfer of data between nodes. The system includes at least one default node and at least two supplemented nodes. Each node has a set of data transfer formats. A default format is included in the format set of each node. Each supplemented node has at least one supplemental format. Transfer format selection means in the form of circuitry and software provides for the selection of a data transfer format which is included in the source node format set and the destination node format set and is compatible with the communication medium. The source node includes a cache of node format sets. The source node searches for the destination node format set in the source node cache and selects a format which is common to the format sets of the source node and destination node.

Abstract: This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time.

Abstract: Software driven controller emulator includes hardware apparatus for emulating the controller at a speed faster than the software driven emulator, incorporating predicting a next event to be emulated and preactivating dedicated logic to emulate the controller driving the next event. In case of errors, the hardware controller sets a code signal and returns emulation to the software driven emulator for error recovery identified by the code signal.

Abstract: Data divided by delimiters representing the boundaries of the data is stored in a data memory. Instructions each including designation of a delimiter are stored in an instruction register. A control circuit decodes an instruction output from the instruction register, and repeats processing of the data read out from the data memory in accordance with the decoded instruction every time the data is read out therefrom. A delimiter detector outputs a coincidence signal when it detects that a delimiter which coincides with the delimiter in the instruction is present in the data read out from the data memory. When this coincidence signal is input to the control circuit, the control circuit ends the processing which has been performed in accordance with the instruction.

Abstract: An improved method and system for transferring control in a multitasking computer system is provided. In preferred embodiments for use with 80386 machines, the virtual machine monitor (VMM) writes a virtual machine break point (VMBP) instruction into the executable code of selected DOS routines to cause the DOS routines to transfer control to the VMM. By selecting systems calls of indefinite duration for the application of this method, system performance can be improved. In this preferred embodiment for 80386 machines, 8086 programs designed to run under DOS can be more efficiently executed in a multitasking environment.

Abstract: Any host requesting acccess to the bus must, on its first attempt, wait for N arbitration delay periods after the bus becomes available before attempting to take control of the bus. If another host takes the bus before completion of the arbitration delay period, the host must wait till the next time the bus becomes available. The arbitration delay count is decreased by one for each successive attempt, until the host either gains control of the bus or the aribration delay period goes to zero. At this point it may attempt to take control of the bus as soon as the bus becomes available. If another higher priority host reaches an arbitration delay count of zero during the same arbitration delay count period, the host will be denied and will wait for the next time the bus becomes available, again with an arbitration delay count of zero.

Abstract: An apparatus and method for furnishing the identification of potential customers that may be interested in a specific product in response to a search request. A first database contains information on, for instance, books and serials in print, in which each individual book or serial is classified. Individuals requesting information regarding specific books or serials identify themselves, along with their product interests. A second database is built up on the first enquirers, including their identification and product interests. The second database enables book publishers to determine the identification of potential customers and of their specific product interests.

Abstract: A computer constructed in accordance with the invention includes at least one transmitting and two receiving structural components. At least the receiving structural components are connected with one another by connecting lines that are arranged in parallel with one another. These connecting lines include data lines and also addressing lines by which each of at least the receiving structural components can be uniquely addressed. When addressed by the appropriate addressing signal, the respective receiving structural component reads the data that is then present at the data lines. A decoder is provided in the transmitting structural component. This decoder is operative for decoding the addressing lines which respectively address the receiving structural components in such a manner that simultaneous addressing of several structural components is possible. The receiving structural components are connected with one another and with the transmitting structural component by a common feedback line.

Abstract: A method is disclosed for dynamically redefining a shell structure which includes embedded formatting, processing or resource information. The shell structure includes end user requirements necessary to process constructs within a data stream which are accessed by means of embedded tags within the data stream. Data stream clutter is reduced and end user formatting is rendered more flexible by embedding tags in the data stream to a point in one or more shells accessible by the end user's work station; however, it is often desirable to modify a particular shell for a specific application without permanently altering the shell. A formatting shell fragment is created in accordance with the present invention which includes a reference to a complete shell and a temporary modification to be applied to that shell. In a preferred embodiment of the present invention multiple formatting shell fragments may be concatenated with other formatting shell fragments and a complete shell.

Abstract: A method for scheduling time initiated tasks from an Intelligent Work Station (IWS) of an SNA network in which a host processor has created a plurality of run ready virtual machines which are assigned under control of a Virtual Machine Pool Manager in response to an LU 6.2 allocate verb to establish an LU 6.2 conversation between distributed parts of an application program, one part of which is resident at the IWS and the other part of which is resident at the host. A distributed application program named BATCH is provided, Part A of which is resident on the user's IWS and Part B of which is resident on the host processor. Part B is functionally a component of Virtual Machine Pool Manager (VMPM). The BATCH program allows the user to tranfer information regarding the task that is to be initiated at a designated time, to the host processor.

Abstract: A mixed hardware register and memory architecture is provided by the present invention to maintain the advantage of variable length stack frames while eliminating the requirement for a stack pointer. The invention includes a global register bank and a stack register bank with two independent address means for addressing the global and stack register banks. Registers are provided as temporary memories for the source operand and destination operand, and a second data path is provided for transfer of data words directly from memory to the local and global registers. The frame pointer is incorporated as a portion of the status register present in the global register bank. Storage of the status register on a call instruction and restore of the status register in a return instruction automatically stores the frame pointer providing the elimination of a hardware register and one cycle in both call and return instructions over prior art devices.

Abstract: In processing a sequence program for a normally closed contact, the input signal is logically inverted before processing, inversion not being required for a normally open contact. A logical inversion circuit is provided for logically inverting an input signal corresponding to the normally closed contact designation of the sequence program before the input signal is fed to a central processing unit, so that inversion processing in the central processing unit can be dispensed with and the operation speed can be increased. The application of a logical inversion signal to the logical inversion circuit can readily be effected by utilizing an address line of the central processing unit.