Abstract: A display device includes a first substrate, an organic light emitting element on the first substrate and including a first electrode, an organic light emitting layer, and a second electrode, a pixel defining layer surrounding the first electrode, a thin film encapsulation layer, and a capping layer on the thin film encapsulation layer. The capping layer may include two reflective interfaces adjacent the light emission or pixel area spaced apart from one another in a plane view. The reflective interfaces may include a boundary between high and low refractive index materials and/or a reflective layer.

Abstract: A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, and a lower gradient portion in which the concentration decreases from the maximum portion to a drift region. When a full width at half maximum determined by setting a depth position of the maximum portion as a range of impurity implantation with reference to a range-full width at half maximum characteristic according to a material of the substrate and a type of impurities contained in the accumulation region is set as a standard full width at half maximum, a full width at half maximum of the distribution in the accumulation region is 2.2 times the standard full width at half maximum or greater.

Abstract: A semiconductor device having an IE-type IGBT structure comprises a stripe-shaped trench gate and a stripe-shaped trench emitter arranged to face the trench gate formed in a semiconductor substrate. The semiconductor device further comprises an N-type emitter layer and a P-type base layer both surrounded by the trench gate and the trench emitter formed in the semiconductor substrate. The semiconductor device also comprises a P-type base contact layer arranged on one side of the trench emitter and formed in the semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrode. The trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.

Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.

Abstract: When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A pixel structure. The pixel structure includes a base substrate; an insulating island on the base substrate; a light emitting element on a side of the insulating island away from the base substrate; an insulating layer on the base substrate and surrounding the insulating island, the insulating layer spaced apart from the insulating island by a groove; and a reflective layer on a lateral side of the insulating layer surrounding a periphery of the light emitting element, and configured to reflect light laterally emitted from the light emitting element to exit from a light emitting surface of the pixel structure. The insulating layer has a height relative to a main surface of the base substrate greater than a height of the insulating island relative to the main surface of the base substrate. The reflective layer is in direct contact with the base substrate in the groove.

Abstract: Disclosed is a display apparatus including a transistor substrate including an emission part overlapping a plurality of organic light emitting devices and a peripheral part surrounding the emission part, a plurality of color filters disposed to respectively correspond to the plurality of organic light emitting devices at the emission part, and a plurality of spacer members spaced apart from one another and disposed to surround the plurality of organic light emitting devices at the peripheral part. Accordingly, the display apparatus is protected from an external impact, and heat transferred to the inside of the display apparatus is easily dissipated to the outside.

Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package featuring a flat plate having a raised edge around its perimeter serving as an anti-stiction device, and an associated method of formation. A CMOS IC is provided having a dielectric structure surrounding a plurality of conductive interconnect layers disposed over a CMOS substrate. A MEMS IC is bonded to the dielectric structure such that it forms a cavity with a lowered central portion the dielectric structure, and the MEMS IC includes a movable mass that is arranged within the cavity. The CMOS IC includes an anti-stiction plate disposed under the movable mass. The anti-stiction plate is made of a conductive material and has a raised edge surrounding at least a part of a perimeter of a substantially planar upper surface.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

Abstract: A flexible display screen and a flexible display apparatus are provided. The flexible display screen includes a display device, a flexible substrate, a support structure and a drive chip. The display device is positioned on the flexible substrate, and the flexible substrate is positioned on the support structure. The support structure further defines a groove thereon to accommodate the drive chip.

Abstract: An array substrate and a method for producing the same are disclosed. The array substrate includes a metal pattern and an electrically conductive pattern sequentially formed on a base substrate, the electrically conductive pattern being insulated from the metal pattern. The array substrate further includes a static charge releasing pattern formed in a same layer and made of a same material as the electrically conductive pattern, and which is insulated from the electrically conductive pattern. The metal pattern is a signal line running through a display area of the array substrate, and includes an input end, an output end, and a body portion between the input end and the output end. The output end of the signal line includes an island-like structure, and a width of the island-like structure is greater than that of the body portion. The static charge releasing pattern is electrically connected with the island-like structure.

Abstract: The present disclosure relates to a light-emitting diode including a first electrode and a second electrode facing each other; an electron transfer layer between the first electrode and the second electrode; and a light emitting material between the first electrode and the second electrode, wherein the electron transfer layer consists of anisotropic nanorods, and the long axes of the anisotropic nanorods are arranged at an angle of about 20 degrees to about 90 degrees with respect to an interface with an adjacent layer into which electrons are injected.

Abstract: A thin film transistor is disposed on a substrate. A via insulating layer having a via hole covers the thin film transistor. A pixel electrode is disposed on the via insulating layer and electrically connected to the thin film transistor through the via hole. A first protection layer surrounds the pixel electrode. A pixel-defining layer covers an edge region of the pixel electrode and at least a portion of the first protection layer. The pixel-defining layer includes an opening through which an upper surface of the pixel electrode is exposed. An opposite electrode faces the pixel electrode. An intermediate layer is disposed between the pixel electrode and the opposite electrode.

Abstract: The present invention provides an OLED display panel and a display device. The OLED display panel includes a luminescent substrate having a first luminescent region and a bending region, and an encapsulated thin film being disposed on the luminescent substrate. The encapsulated thin film disposes a first optical device therein. The projection of the first optical device on the luminescent substrate is at the junction of the first luminescent region and the bending region, to make light from the first luminescent region enter into the bending region by aid of the first optical device.

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

Abstract: An organic light-emitting display device including: a substrate; a pixel electrode on the substrate; a pixel defining film on the pixel electrode and having a first opening at least partially exposing the pixel electrode; an organic light-emitting layer on the exposed portion of the pixel electrode; a common electrode on the organic light-emitting layer and the pixel defining film; an encapsulation layer on the common electrode; a black matrix on the encapsulation layer and having a second opening overlapping the first opening; and a plurality of first sensing lines on the black matrix and surrounding the pixel electrode in a plan view to define a pixel region. At least portions of the first sensing lines defining the pixel region do not overlap the common electrode in the pixel region to reduce the common electrode's influence on the touch sensing lines and improve touch sensitivity.