Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: An organic light emitting display device that includes a substrate that may be flexible, and an insulation layer arranged on the substrate. The insulation layer is perforated by openings to facilitate bending of the display device. A plurality of the connection lines extend from the image producing display area to a peripheral area of the display device to allow for connection to an external device. Each of the openings includes one of the connection lines to prevent shorting together of the connection hues during the patterning step used to pattern the connection lines. In one embodiment, the each of the connection lines extends through the openings and across the sidewalls of the openings. In another embodiment, the connection lines are interposed between two adjacent openings.

Abstract: A display apparatus comprises a first substrate comprising a first external surface and a first internal surface; a second substrate having a second external surface and a second internal surface facing the first internal surface of the first substrate; and a display unit disposed between the first and second substrates and comprising an array of pixels. The first substrate comprises a first side connecting the first external surface and the first internal surface. In a cross section perpendicular to the first external surface, the first side comprises a first straight region and a first curved region located between the first straight region and the first internal surface. The second substrate comprises a second side connecting the second external surface and the second internal surface. The second side comprises a second straight region and a second curved region located between the second straight region and the second internal surface.

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

Abstract: The present disclosure describes a flexible display apparatus that includes a display substrate including a light-emitting area, and a non-emitting area including a bending area foldable in a folding direction outside of the light-emitting area, and a pad area outside of the bending area, a thin film encapsulation layer over the light-emitting area, and a driver inside a curvature portion of the display substrate at the bending area, and including a plurality of driving terminals electrically connected to a plurality of pad terminals in the pad area through penetration wirings in via holes defined by the display substrate to provide a new, thinner flexible display apparatus.

Abstract: The present technology relates to a solid-state imaging device, a method of manufacturing the same, and an electronic device capable of improving sensitivity in a certain wavelength band and at the same time reducing color mixture of light of other wavelength bands in a photoelectric conversion unit.

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Abstract: Disclosed is an organic light emitting display device including a plurality of sub-pixels on an array substrate in which each sub-pixel includes a circuit part including a switching transistor, a driving transistor and a capacitor; and a light emitting part having a shape defined with a width and a length and including a first electrode electrically connected to the driving transistor, an organic light emitting layer and a second electrode, the first electrode including a first pattern having a recess, a second pattern having a protrusion received in the recess, and a third pattern connecting the first and second patterns, wherein a depth of the recess is greater than a half of a longer of the width and the length of the light emitting part.

Abstract: Provided is an organic light-emitting element for emitting white light in which an optical distance L1 between a first emission layer (52) and a reflective electrode (80) satisfies Expression (a), and an optical distance L2 between a second emission layer (72) and the reflective electrode (80) satisfies Expression (b): (?1/8)×(3?(2?1/?))<L1<(?1/8)×(5?(2?1/?))??(a); and (?2/8)×(?(2?2/?)?1)<L2<(?2/8)×(?(2?2/?)+1)??(b), and in which a refractive index of a first charge transport layer (51) formed between a light extraction electrode (4) and the first emission layer (52) at the wavelength ?1 is 1.70 or less.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A planar Hall effect element be formed upon or can include a P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hail effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.

Abstract: An organic EL display device includes a substrate and an organic EL element (electroluminescent element) provided on the substrate. The organic El display device includes a sealing layer that seals the organic EL element. The sealing layer includes silicon oxide films. Moreover, the degree of oxidation of the silicon oxide films is set to 1.2 or more and 1.8 or less.

Abstract: A display apparatus includes a substrate having a first area, a second area, and a third area, the second area being between the first and third areas, a display unit on the substrate in the first area, and an encapsulation layer covering the display unit in the first area and extending into the second area, the encapsulation layer including a first inorganic layer, a second inorganic layer, an organic layer between the first and second inorganic layers in the first area, and a plurality of organic patterns spaced apart from each other at certain intervals in the second area. The first and third areas of the substrate are bent with respect to each other at a predetermined angle, other than a straight angle, with the second area bent therebetween, and the plurality of organic patterns are in the second area that is bent toward the bottom of the substrate.

Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Abstract: A fingerprint identification device and a manufacturing method thereof, an array substrate and a display apparatus are provided. The fingerprint identification device comprises first gate lines and read signal lines. The first gate lines and the read signal lines intersect with each other to define a plurality of fingerprint identification units, and each fingerprint identification unit is provided with a photosensitive element and a first transistor. The photosensitive element includes a first electrode layer, and a first doped semiconductor layer, a second doped semiconductor layer and a second electrode layer which are sequentially positioned on a surface of the first electrode layer.

Abstract: This disclosure provides an OLED light-emitting device, a production method thereof as well as a display apparatus, and relates to the technical field of OLED display, which can enhance the internal quantum efficiency of a blue OLED light-emitting device. This OLED light-emitting device comprises a substrate, and an anode, a hole transport layer, a blue light-emitting layer and a cathode provided on the substrate; the OLED light-emitting device further comprises an Ag nanolayer located between the anode and the hole transport layer; wherein the blue light-emitting layer is a blue phosphorescent light-emitting layer; the absorption spectrum of the Ag nanolayer overlaps the emission spectrum of the blue phosphorescent light-emitting layer, and the blue phosphorescent light-emitting layer is located within the penetration depth of surface plasma of Ag nanoparticles in the Ag nanolayer. It is used in the production of a blue OLED light-emitting device and a display apparatus comprising the same.

Abstract: Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.

Abstract: This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.