Abstract: When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

Abstract: According to one embodiment, a display device includes an insulating substrate, a light-shielding member disposed above the insulating substrate, a first color filter disposed above the insulating substrate, a second color filter disposed alongside the first color filter, a partition disposed on the light-shielding member and between the first color filter and the second color filter and an insulating film disposed on the first color filter and the second color filter, and an upper surface of the partition and an upper surface of the insulating film are located on a same plane.

Abstract: The present disclosure relates to a memory device having a hybrid insulating layer and a method for preparing the same. In detail, a memory device including a gate electrode on a substrate, a source electrode, and a drain electrode has a hybrid memory insulating layer between the gate electrode and the source and drain electrodes that is polarizable and includes a mixed material of vinyltriethoxysilane and organic matter to lead to hysteresis. According to the present disclosure, a memory insulating layer is formed as a hybrid insulating layer including a mixture of polyvinylphenol as the organic matter and vinyltriethoxysilane to complement the properties of an organic memory whereby increasing memory performance, and it stably operates at both low and high temperatures whereby having a wide usage range.

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Abstract: A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Abstract: An optoelectronic semiconductor device, a method for manufacturing an optoelectronic semiconductor device and light source having an optoelectronic semiconductor device are disclosed.

Abstract: An organic light emitting diode display that maintains a luminance distribution characteristic of each pixel at the side substantially similar to a luminance distribution characteristic of each pixel at the front of the OLED display by improving a twist of a lateral color with respect to a front color. The organic light emitting diode display includes a substrate, a driving wire disposed on the substrate, a color filter disposed on the driving wire. The color filter includes a blue color filter, a red color filter, and a green color filter formed on the driving wire; and an organic light emitting diode disposed on the color filter, where a recess portion is defined at a lower surface of the blue color filter, and a convex portion is defined at a lower surface of the red color filter or the green color filter.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.

Abstract: An oxide semiconductor film with a low density of defect states is formed. In addition, an oxide semiconductor film with a low impurity concentration is formed. Electrical characteristics of a semiconductor device or the like using an oxide semiconductor film is improved. A semiconductor device including a capacitor, a resistor, or a transistor having a metal oxide film that includes a region; with a transmission electron diffraction measurement apparatus, a diffraction pattern with luminescent spots indicating alignment is observed in 70% or more and less than 100% of the region when an observation area is changed one-dimensionally within a range of 300 nm.

Abstract: An array substrate includes a metal pattern and an electrically conductive pattern formed sequentially on a base substrate. The electrically conductive pattern is insulated from the metal pattern; and a static charge releasing pattern is formed in a same layer as the electrically conductive pattern and formed by a same material as the electrically conductive pattern, the static charge releasing pattern being insulated from the electrically conductive pattern and electrically connected with the metal pattern.

Abstract: A flexible organic light emitting display (OLED) device includes an organic emitting diode on a flexible substrate, an encapsulation film covering the organic emitting diode and including a first inorganic layer and an organic layer. The first inorganic layer is formed of a first material, and at least a portion of the first inorganic layer includes a dopant that increases the surface energy of the doped material compared to that of non-doped material.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.

Abstract: A resin composition including an olefin resin, an alkenyl-containing alkoxy silane compound, and at least one inorganic filler selected from the group consisting of titanium oxide, alumina, talc, clay, aluminum, aluminum hydroxide, mica, iron oxide, graphite, carbon black, calcium carbonate, zinc sulfide, zinc oxide, barium sulfate, and potassium titanate; a reflector using the resin composition; a reflector-bearing lead frame; and a semiconductor light-emitting device. Accordingly, provided by the present invention are: a resin composition capable of expressing an excellent heat resistance (especially heat distortion resistance) even when it is made to a formed body; a reflector using the resin composition; a reflector-bearing lead frame; and a semiconductor light-emitting device.

Abstract: Disclosed herein is a transparent organic light-emitting display (OLED) device. A first sub-pixel includes a first transparent region and a first emissive region disposed in line with the first transparent region in a first direction, and a second sub-pixel includes a second transparent region area and a second emissive region in line with the second transparent region in the first direction. The second sub-pixel is disposed adjacent to the first sub-pixel in the second direction. The first emissive region is in line with the second transparent region in a second direction, and the second emissive region is in line with the first transparent region in the second direction. In the transparent OLED device according to an exemplary embodiment of the present disclosure, emissive regions are disposed in a zigzag pattern with respect to a gate line, so that the area of the transparent regions can be enlarged, and accordingly higher transmittance can be achieved.

Abstract: The present invention discloses a wireless package with a resilient connector for connecting a substrate to an antenna. The antenna is disposed directly on a top surface of a molding compound of the wireless package. The resilient connector has a lower terminal bonded to the substrate, a horizontal contact portion, and an oblique support portion integrally extending between the horizontal contact portion and the lower terminal. The horizontal contact portion has a flat top surface that is coplanar with the top surface of the molding compound and is in direct contact with the antenna such that the contact resistance distribution is concentrated and the production yield of the wireless package is improved.

Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.

Abstract: An organic light-emitting device includes a substrate, a bottom electrode on the substrate, an organic light-emitting layer on the bottom electrode, and a top electrode on the organic light-emitting layer, wherein the top electrode includes a first electrode part, a grid-shaped or plate-shaped second electrode part on the first electrode part, and an adhesive layer on the second electrode part. The organic light-emitting device includes the top electrode that has low sheet resistance. The top electrode includes a graphene layer as the first electrode part.

Abstract: A first conductive line is positioned outside a display area of a substrate. A passivation layer covers a portion of the first conductive line. A first connection line is positioned on the passivation layer, contacting the first conductive line. An insulation layer having at least one opening is positioned on the passivation layer and the first connection line. A second connection line is positioned on the insulation layer. The second connection line contacts the first connection line via the at least one opening and has an end portion that contacts the first conductive line. A second conductive line is positioned between the display area and the first conductive line, overlapping the first connection line and including a hole. The hole of the second conductive line overlaps one of the at least one opening. The passivation layer is interposed between the second conductive line and the first connection line.

Abstract: A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.