Abstract: An AC electronic solid-state switch includes an electrically insulating and thermally conductive layer, a first electrically conductive trace, a second electrically conductive trace, and a plurality of semiconductor dies each electrically connected to the first electrically conductive trace and the second electrically conductive trace. Each of the plurality of semiconductor dies forms a MOSFET, IGBT or other types of electronically controllable switch. The AC electronic solid-state switch further includes a common drain conductor that is electrically connected to each drain terminal of the plurality of semiconductor dies. The AC electronic solid-state switch is configured to block between 650 volts and 1700 volts in the off-state in a first direction and a second direction, the second direction being opposite the first direction, and the AC electronic solid-state switch is configured to carry at least 500 A continuously in the on-state with a voltage drop of less than 2V.

Abstract: A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region. A second insulation pattern is disposed over the second region of the semiconductor region. The second insulation pattern has a thickness greater than a thickness of the first insulation pattern. A gate electrode is disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.

Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.

Abstract: A single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

Abstract: A method for engineering a line shape of emission spectrum of an organic emissive material in an electroluminescent device is disclosed in which a layer of plasmonic metallic nanostructures having a localized surface plasmonic resonance (LSPR) is provided in proximity to the emissive layer and the layer of plasmonic metallic nanostructures is greater than 2 nm but less than 100 nm from the emissive layer and the LSPR of the plasmonic metallic nanostructures matches the emission wavelength of the organic emissive material. An electroluminescent device incorporating the plasmonic metallic nanostructures is also disclosed.

Abstract: An organic light emitting display device and a method for manufacturing the same are disclosed. The organic light emitting display device includes a substrate divided into an emission area and a non-emission area, an overcoat layer disposed on the substrate and including a plurality of micro lenses in the emission area, a first electrode disposed on the overcoat layer and disposed in the emission area, an organic emission layer disposed on the substrate and having at least one layer which is flatly formed in the emission area, and a second electrode disposed on the organic emission layer.

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

Abstract: Disclosed is an organic light emitting diode display device. The disclosed organic light emitting diode display device includes an overcoat layer disposed on a substrate that is divided into an emissive area and a non-emissive area, and has multiple micro lenses in the emissive area and at least one depression in the non-emissive area. The organic light emitting diode display device further includes: a first electrode disposed on the overcoat layer, wherein the first electrode is disposed in the entire emissive area and in a part of the non-emissive area; a bank pattern disposed in the non-emissive area so as to be superposed on the depression; an organic light emitting layer disposed on the substrate; and a second electrode disposed on the organic light emitting layer. Accordingly, the organic light emitting diode display device may prevent light leakage.

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.

Abstract: A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate. An important aspect in development of the semiconductor chip package is improvement of connections between different components within the package.

Abstract: A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material. The rough interface includes a plurality of protruded portions and a plurality of recessed portions.

Abstract: An organic light emitting diode display device comprises a substrate which includes a plurality of pixel regions each having a sub-pixel region and a transparent region. In each pixel region, an active layer is disposed in the sub-pixel region. A gate electrode overlaps the active layer. A first electrode is disposed on the active layer, and contacts the active layer. A second electrode is spaced apart from the first electrode, and contacts the active layer. A first lower electrode having a first thickness is disposed in the sub-pixel region and connected to the second electrode. A second lower electrode is disposed in the transparent region on the substrate, located at a same level as the gate electrode. The second lower electrode has a second thickness that is less than the first thickness, and is transparent.

Abstract: A solid-state imaging device, for reduction of reflection of incident light at a sidewall surface of a light blocking layer of each phase difference detection pixel, includes: a normal pixel for generating a pixel signal; and a phase difference detection pixel for generating a phase difference signal for image plane phase difference AF. In this solid-state imaging device, the normal pixel and the phase difference detection pixel each include a photoelectric conversion layer and a lens for gathering incident light onto the photoelectric conversion layer, the phase difference detection pixel includes a light blocking layer having an apertural portion with an aperture deviating from the optical axis of the lens, and an antireflection portion that prevents reflection of the incident light gathered by the lens unit is formed on the light blocking layer. The present disclosure can be applied to back-illuminated CISs.

Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: An array substrate has a display area and a non-display area disposed at a periphery of the display area. The array substrate includes: a base substrate; at least one gate driver on array (GOA) circuit disposed on the base substrate and disposed in the non-display area; a planarization layer disposed on a side of the at least one GOA circuit facing away from the base substrate; and at least one electrostatic protection portion disposed on a surface of the planarization layer facing away from the base substrate and disposed in the non-display area. An orthographic projection of each GOA circuit on the base substrate is located within an outer boundary of an orthographic projection of a corresponding electrostatic protection portion on the base substrate.