Abstract: A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

Abstract: A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.

Abstract: A temporally normalized processor utilization trace is generated.

Abstract: A data processing apparatus and method for handling interrupts is provided, the apparatus having an interrupt controller operable to receive interrupts generated by a number of interrupt sources, and to determine based on predetermined criteria whether to output an interrupt request signal. A processing unit is provided which is operable upon receipt of the interrupt request signal to perform an interrupt service routine for a selected one of the received interrupts in order to generate an interrupt response for the corresponding interrupt source. Timer logic is also provided which is operable upon receipt of an interrupt generated by an associated interrupt source to produce a timing indication.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: An interface unit is provided for a communication system comprising a master unit and a plurality of slave units serially connecting the master unit via a double ring structure comprising a first communication path and a second communication path. The interface unit comprises a first switching unit, which is configured to output information signals received by the master unit as a first information signal to the first communication path and as a second information signal to the second communication path; and a second switching unit, which is configured to forward the first information signal circulating on the first communication path and second information signal circulating on the second communication path to the master unit.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A device comprising a temperature measurement module, a performance state module, a memory bandwidth module, and a fan speed module. The temperature measurement module is configured to determine a rate of temperature change in a server and to output a control signal when the rate of temperature change is above a threshold rate. The performance state module is configured to reduce a performance state of the device to a lowest system level in response to the control signal, and to reduce a processor power consumption and a subsystem power consumption to a minimum power level in response to reducing the performance state to the lowest system level. The memory bandwidth module is configured to reduce a memory bandwidth to a minimum bandwidth level based on the control signal. The fan speed module is configured to reduce a fan speed to a minimum level based on the control signal.

Abstract: A signal processing device controls a plurality of signal processing units that process an input signal inputted via a signal line with wide bandwidth, via a control line with narrow bandwidth or the signal line, and includes: a storing unit configured to store correspondence information that associates instruction information indicating an instruction of control with respect to each of the signal processing units, with control information related to all of the plurality of signal processing units, among pieces of control information necessary for each of the signal processing units to execute content of control; and a transmitting unit configured to transmit the control information associated with the instruction information by the correspondence information, to the plurality of signal processing units via the signal line, when control is instructed with respect to the plurality of signal processing units.

Abstract: A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.

Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

Abstract: An information processing apparatus transitions from an active state, in which processing according to an application program is executed, to a paused state due to a predetermined trigger, and transitions from the paused state to the active state due to another trigger different from the predetermined trigger, and includes: a usage rate calculating section calculating a usage rate of a main memory, when transition is made from the active state to the paused state; a paused state selecting section selecting a paused state to which transition is to be made from among a plurality of kinds of the paused state, on the basis of a usage rate of the main memory calculated by the usage rate calculating section; and a paused state transition section transitioning itself to a paused state selected by the paused state selecting section.

Abstract: Embodiments are described for executing embedded functions in endpoint devices by proxy in a shared PCI Express subsystem. The shared subsystem comprises a plurality of proxy devices coupled to a PCIe fabric, wherein each one of the proxy devices is associated with an endpoint device and coupled to a controlling server through a PCIe link. An associated proxy device comprises a copy of the configuration space of the target endpoint device. Embedded functions of an endpoint device can be accessed by controlling servers through the associated proxy devices. Devices in the shared subsystem use PCI protocol to communicate. The duplication of the endpoint configuration space in the proxy device is administrated by a proxy configuration manager. The proxy device translates destination addresses in upstream and downstream transactions. A proxy interrupt conveyance mechanism relays interrupt messages from an endpoint device to the controlling server via the associated proxy device.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: A universal series bus (USB) power supply has a DC power source, a USB power interface and a voltage modulation module. The USB power interface is for connecting to an electronic device that stores a default D+ voltage and a default D? voltage. The voltage modulation module connects to and outputs signals to the D+ and D? terminals of the USB power interface. If voltage levels of the output signals are not respectively identical to the default D+ and D? voltages, the voltage modulation module changes the voltage levels of the signals output to the D+ and D? terminals of the USB power interface until the voltage levels of the output signals are respectively identical to the default D+ and D? voltages. Therefore, the USB power supply may be applied to any kind of electronic device that is charged over a USB interface.

Abstract: A method and system for providing services in a network including a control point and plural UPnP devices is provided. Surrogates are used to functionally replace the original UPnP device/service functionalities without new hardware or firmware/software updates. The surrogates enable proper operation in UPnP networks where devices that implement surrogates can coexist in the same network with UPnP devices that do not. This allows updating existing device functionalities without requiring new hardware or firmware/software updates.

Abstract: A data accessing system bridges a first master device and a second master device to a first slave device and a second slave device. The data accessing system includes a register, a first multiplexer, a second multiplexer and a control unit. The amount of data that the first master device can process each cycle is less than which of the second slave device. The data accessing system can solve the problem when the first master device writes data to the second slave device via merging two different data. Also, the data accessing system can solve the problem when the first master device reads data to the second slave device via extracting part of the data.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A method for determining configuration information to be reported comprises accessing a table corresponding to a configuration resource associated with the configuration information, wherein the table comprises an entry for each hardware configuration definition to be built for the configuration resource, identifying a seed value in the table corresponding to the configuration resource, and modifying the seed value based on a result of processing each entry indicated by the table.

Abstract: A system for implementing handshaking configuration to enable coordinated data execution in a computer system. The system includes a core logic component coupled to a system memory and a graphics processor coupled to the core logic component via a graphics bus. The graphics processor and the core logic component implement a configuration communication to selectively configure coordinated data execution between the graphics processor and the core logic component via communication across the graphics bus.