Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract: In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

Abstract: A system and method for providing a serial communication bus is disclosed. A serial communication bus connects multiple footprint devices, such as electronic sensors in a process control sample system. The footprint devices can utilize various footprint device specific communication protocols. Multiple tophat devices act as general I/O ports for connecting with the footprint devices. Each tophat device identifies the footprint device specific communication protocol of a connected footprint device, converts outputs signals transmitted from the connected footprint device from the footprint device specific communication protocol of the footprint device to a standard bus communication protocol, and converts input signals directed to the connected footprint device from the standard bus communication protocol to the footprint device specific communication protocol of the footprint device.

Abstract: Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does not include a request, a different queue slot having the highest static priority and including a request is given access to the resource. The token is advanced to a different queue slot after one or more arbitration cycles. Requests are assigned to the highest priority queue slot, to random or arbitrarily selected queue slots, or based on the source and/or type of the request. One or more queue slots may be received for specific sources or types of requests. Resources include processor access, bus access, cache or system memory interface access, and internal or external interface access.

Abstract: The present invention relates to the field of communications, in particular, to a server for solving the problem related to the incompatibility between normal blades and multi-processing blades in a conventional server. The server according to an embodiment of the invention includes a backboard, on which backboard wiring and a first slot are disposed. At least two second slots are further disposed on the backboard. Both a first interface configured to be connected to a normal blade and a second interface configured to be connected to a multi-processing blade are disposed on each of the second slots, the first interface being connected to a corresponding Cluster Switch interface disposed on the first slot via the backboard wiring, and the second interface being interconnected directly via the backboard wiring or being connected to a corresponding Symmetrical Multi-Processing Switch interface disposed on the first slot via the backboard wiring.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Abstract: A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, identifying an active transaction in the modified schedule list, and providing code data to the USB device from the main memory based on the identified active transaction.

Abstract: Devices, systems and methods for providing a connector system are disclosed. The exemplary device may have system and device flow contacts on the system and device connectors, respectively. A first set contacts and a second set of contacts may be electrically connected to each other to verify that system and device contacts are properly mated to each other. A controller linked to a contact circuit may regulate the power and/or signals provided to an end device.

Abstract: A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.

Abstract: A communication apparatus for communication according to a master-slave communication protocol is formed as a slave instance communicating with a master instance via a bus. The master instance is operative to switch the bus into a bus suspend state if no bus activity is present during a predetermined interval. In response to a bus suspend state, the slave instance makes a transition to a slave suspend state. The communication apparatus includes a monitor configured to monitor the bus activity and a transmitter configured to transmit a signal via the bus if the monitor does not recognize any bus activity during part of the predetermined interval and a transition of the slave instance to the slave suspend state is undesirable, wherein the signal is operative to prevent the master instance from switching the bus into the bus suspend state.

Abstract: A data communication system including a portable electronic device, a server device and a cradle device for mediating transmission and reception of data between the portable electronic device and the server device.

Abstract: A method and a system of controlling access of data items to a shared resource, wherein the data items each is assigned to one of a plurality of priorities, and wherein, when a predetermined number of data items of a priority have been transmitted to the shared resource, that priority will be awaiting, i.e. no further data items are transmitted with that priority, until all lower, non-awaiting priorities have had one or more data items transmitted to the shared resource. In this manner, guarantees services may be obtained for all priorities.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: The present invention unitarily manages the configuration change of a storage system so as to know the latest configuration, and evaluates the reliability in advance when the configuration is changed so that the generation of a failure is suppressed. When the host 1 is connected to the switch 2, the attribute information of HBA 1A and the attribute information of the switch 2 are stored in the connection information storage unit 2C by FDMI (Fabric Device Management Interface) (S1, S2). Each attribute information is associated with each other and is managed as combination information. The storage device 3 acquires the combination information from the switch 2 (S3, S4), and requests the management device 4 to judge the reliability of this combination (S5). The management device 4 judges the combination of the HBA and the switch (S6), and notifies this judgment result to the storage device 3 (S7).

Abstract: An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements.

Abstract: Methods and apparatuses for improving detection of a Serial Advanced Technology Attachment (“SATA”) target device by a storage initiator over a link. The storage initiator receives a Frame Information Structure (“FIS”) and determines whether the FIS is valid. In direct response to a determination that the FIS is invalid, the storage initiator immediately resets the link to the SATA target device.

Abstract: An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies.

Abstract: A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved.

Abstract: In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.