Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: According to one embodiment, a host bus adapter (HBA) is disclosed. The HBA includes a first lookup table to retrieve a remote node index (RNI) based upon an address received from a remote device as a component of an open address frame, a second lookup table to retrieve a remote node context (RNC) based upon the RNI and connection management logic coupled to the second lookup table to control a connection between the HBA and the remote device based upon the RNC.

Abstract: A method to provide more opportunities to close a connection in an orderly fashion and avoid abrupt break of the connection. A device and a system operable to practice such as method.

Abstract: The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.

Abstract: A network bridge with a configuration and control unit. The unit is connected to some or all of the functional components of the network bridge via interfaces. The unit may poll and evaluate data within the functional components, including operating data and/or parameters. The unit may manipulate the data and/or parameters within the functional components, based on the evaluation of that data.

Abstract: Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.

Abstract: Methods for configuring an embedded system are described. One method includes connecting a plurality of add-on cards to a circuit board having a programmable processor. The programmable processor is configured to communicate with the plurality of add-on cards. At least one add-on card connects to a circuit board utilizing two or more connectors. The method also includes determining an identifier of each of the plurality of add-on cards, where the identifier of each of the plurality of add-on cards is used to generate a configuration image. Further included is configuring the programmable processor to communicate with the plurality of add-on cards by obtaining the configuration image. In some examples, the programmable processor is an FPGA.

Abstract: In at least some embodiments, a method comprises emulating a Universal Serial Bus (USB) host controller at a computer system. The method further comprises using the emulated USB host controller to interface a remote management console with the computer system.

Abstract: Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described.

Abstract: Technologies are described for implementing locks to control I/O operations in a storage system. The lock implementations can have reduced resource requirements for memory and processing. Through the utilization of the technologies and concepts presented herein, an I/O process preparing to acquire a write lock can advertise its need for the lock for a pre-determined time before the lock is granted. The time period for advertisement can be specified so that all I/O operations that were initiated before the advertisement are guaranteed to have completed by the time the advertisement period is over. As such, a lock controller may only need to track outstanding I/Os that begin once the advertisement starts. This can reduce the typical requirement to maintain and process a lock structure for every unit of storage in the system at all times.

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.

Abstract: A resource-lock monitor detects when processors in a multi-processor system are stuck waiting for access to a shared resource. A lock-monitor register has a lock bit and a sticky-lock bit for each processor being monitored. The lock and the sticky-lock bits are both set when the processor executes a lock instruction that also sends a lock-request to a resource arbiter. The lock bit is cleared when the resource arbiter grants access to the processor, but the sticky-lock bit remains set until sticky-lock bits are cleared by monitoring software at the end of a monitoring period. At the end of each monitoring period, monitoring software reads the lock and sticky-lock bits and finds a locked processor when a processor's lock bit is still set, but its sticky-lock bit is cleared. When the locked processor remains locked at the end of another monitoring period, an error handler resets the locked processor.

Abstract: A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.

Abstract: A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT) environment. In some embodiments, the custom interrupt service routine does not in any way interfere with the operation of the interrupt handling in a non-VT environment.

Abstract: An integrated circuit enables interconnection of a serial digital bus with a microcontroller unit. A physical interface provides for the transmission and reception of messages over the serial digital bus. A communication interface includes a serial interface for communicating with the microcontroller unit. The communication's interface further extracts clock data and information data from the received messages from the serial data bus in a format that may be transmitted to the microcontroller unit via the serial interface. The communication interface further formats data received from the serial interface into messages for transmission onto the serial digital bus. A sync timing generator generates a sync pulse for synchronizing the microcontroller unit with the serial interface of the communication interface.

Abstract: Embodiments of a method and apparatus for controlling a personal computer are provided that can stably engage and disengage a bay device to a single IDE channel coupled to a main memory. An embodiment of a portable computer can include an integrated drive electronic (IDE) controller supporting a single IDE channel, a main memory and a bay device connected to the IDE channel, and a control device that can set the IDE channel in a tri-state and reset (e.g., restore) the connection to the IDE channel as the bay device is attached to and detached from a bay.

Abstract: System and method for managing routing of data in a distributed computing system, such as a distributed computing system that uses PCI Express protocol to communicate over an I/O fabric. A physical tree that is indicative of a physical configuration of the distributed computing system is determined, and a virtual tree is created from the physical tree. The virtual tree is then modified to change an association between at least one source device and at least one target device in the virtual tree. A validation mechanism validates the changed association between the at least one source device and the at least one target device to enable routing of data from the at least one source device to the at least one target device.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.