Abstract: The method and system for data transfer between the master device and the slave device through the bus are presented.

Abstract: A digital multimedia device capable of functioning as both a portable multimedia player (PMP) and a notebook computer is provided. The digital multimedia device includes: a computer unit including a body, a first processor included in the body to operate a first operating system (OS), a first display unit for displaying image information processed by the first processor, and a first input unit; a PMP unit including a second processor to operate a second operating system, a hard disk drive (HDD) for storing programs and data, a second display unit for displaying image information processed by the second processor, and a second input unit; and a docking unit disposed in the computer unit and the PMP unit for docking the PMP unit to the computer unit, wherein, when the PMP unit is docked with the computer unit, the computer unit shares the HDD with the PMP unit to perform processing operations, and the PMP unit operates independently or in association with the computer unit.

Abstract: A method for operating an expansion card of a computer is proposed, said computer having at least one slot for accommodating the expansion card, wherein there is stored in a memory area of the expansion card a first and a second configuration data record, one of which is assigned to a first and the other to a second signaling voltage, and wherein the configuration data records transmitted to a FPGA chip of the expansion card indicate to the FPGA chip whether a protection circuit is to be activated or deactivated. Suitable measures enable functional units of a PCI expansion card suitable for both a 3.3 V and a 5 V signaling voltage to be integrated in an FPGA together with a PCI controller, the expansion card being supplied or suppliable with an external voltage independently of a signaling voltage of a computer or basic system.

Abstract: An apparatus, system, and method are disclosed for resetting an inter-integrated circuit (I2C) bus slave. A data line resistor in series is provided with a data line of an I2C bus in communication with the I2C bus slave. A clock line resistor in series is provided with a clock line of the I2C bus. A data line differential amplifier detects a first specified voltage across the data line resistor and a clock line differential amplifier detects a second specified voltage across the clock line resistor wherein the first specified voltage is substantially equal to a data line resistor resistance multiplied by a specified current and the second specified voltage is substantially equal to a clock line resistor resistance multiplied by the specified current. A time module detects the first and second specified voltage for a specified time interval. A reset module resets the I2C bus slave in response detecting the first and second specified voltage for the specified time interval.

Abstract: An apparatus, system, and method are disclosed for resetting an inter-integrated circuit (I2C) data line with negative voltage. A hang detection module detects an I2C hung line selected from a data line and a clock line wherein an I2C bus master and I2C bus slave communicate over the data line and the clock line. In response to the detected hung line, a negative voltage generator drives the data line to a specified negative voltage for a specified time interval. A clamp diode clamps the voltage of the data line to greater than a specified limit. On receiving the specified negative voltage, a voltage detector module detects the specified negative voltage of the data line. A timer module detects the specified negative voltage for the specified time interval. In response to detecting the specified negative voltage for the specified time interval, a reset module resets the I2C bus slave.

Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.

Abstract: An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

Abstract: A bus system including first and second blocks. The bus system is configured such that data may be transferred at the first block at the same time that data may be transferred at the second block.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

Abstract: A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Abstract: A method for data access via an inter-integrated circuit (I2C) protocol. The method includes receiving an I2C read command at an I2C slave device, where the I2C read command is from an I2C master device. The method also includes reading stored data from a storage device in response to receiving an I2C read command. The stored data is at a first location in the storage device corresponding to a value in a register array pointer in the I2C slave device. The stored data is transmitted to the I2C master device in response to the reading. The method also includes receiving an I2C write command at the I2C slave device, where the I2C write command is from the I2C master device and the write command includes master data and a slave device register address. The master data is written to the storage device in response to receiving the I2C write command, with the master data being written at a second location in the storage device corresponding to the slave device register address.

Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.

Abstract: A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: A method for handling multiple system management interrupt (SMI) events in a multiprocessor system. The method comprises a first set of one or more processors in the multiprocessor system receiving a first SMI event. The first set of processors then enter an SMI handler for the first SMI event. The method further comprising determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event, and scheduling a second SMI event based upon the content of the first SMI event. The first set of processors each exit the SMI handler for the first SMI event without handling the first SMI event. Preferably, the method includes handling the second SMI event as a result of determining that all of the active processors in the multiprocessor system are in the SMI handler for the second SMI event.

Abstract: An image recorder for recording image data into a recording medium and supplying the image data recorded into the recording medium to a connected host through a predetermined communication interface, according to one of a plurality of different communication specifications, includes: a device configured to notify the host of information indicating a plurality of different usable communication specifications, in reply to a request from the host; a device configured to check the communication specification specified by the host, according to a return from the host based on the information indicating the different usable communication specifications notified by the notifying device; and a device configured to supply the image data recorded in the recording medium to the host through the predetermined communication interface, according to the communication specification checked by the checking device.

Abstract: Embodiments provide an efficient system of device configuration and detection for a peripheral component interconnect (PCI) system. Each connected device provides a descriptor and is accessed at a predetermined address. The device is then configured by the operating system based on the device descriptor and assigned a device address for further operation. The system also supports the assignment of devices to different partitions in the computer system.

Abstract: A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.

Abstract: A Universal Serial Bus (USB) device for exchanging data with a USB host connected via a USB cable is provided. In a USB device for exchanging data with a USB host connected via a USB cable, the USB device comprises a USB encoder for outputting USB encoding data; a reset controller for generating a reset control signal that is activated in a predetermined logic level when the USB device needs to be reset; and a data output unit for selecting and outputting one of the USB encoding data and the logic low signal, in response to the reset control signal. According to the USB device of the present invention, the user need not physically disconnect the USB cable. Instead, the user manually selects the reset of the USB device from the programs of the PC that includes the USB host. In addition, the automatic program saved in the system equipped with the USB device helps to implement the reset operation of the USB device automatically when a predetermined situation occurs.