Abstract: An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

Abstract: There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted to the bus of the respective bus system in its own cycle. A predetermined or predeterminable number of data items is buffered from a data sequence that is to be transmitted from the original bus system to the target bus system, and a respective data item is determined on the basis of the cycle time TB of the target bus system from the data buffered on the basis of cycle time TA of the original bus system.

Abstract: Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Abstract: An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.

Abstract: In one embodiment, a solution is provided wherein a lock client sends lock requests to a lock manager upon receipt of an input/output (I/O) and receives back a lock grant. At some point later, the lock client may send a lock release. The lock manager, upon receipt of a lock release from a lock client, remove a first lock request corresponding to the lock release from a lock grant queue corresponding to the lock manager. Then, for each dependency queue lock request in a dependency queue corresponding to the first lock request, the lock manager may determine whether the dependency queue lock request conflicts with a second lock request in the lock grant queue, and then may process the dependency queue lock request according to whether the dependency queue lock requires conflicts with a second lock request in the lock grant queue.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.

Abstract: In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.

Abstract: An USB matrix switch system provided for a plurality of USB devices shared with a plurality of hosts is disclosed.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

Abstract: A slot interface access device including a slot management module; a slot control module; and a physical slot to management slot contrast table, the slot management module, the slot control module, and the physical slot to management slot contrast table being provided between an input and output control module and a slot interface lower than the input and output control module. The input and output control module accesses the slot interface using virtual slot identification information. The slot management module converts the virtual slot identification information into physical slot identification information while referring to the physical slot to management slot contrast table, and accesses the slot control module corresponding to the physical slot identification information obtained by conversion, thereby realizing a physical access of the input and output control module to the slot interface.

Abstract: A slot interface access device including a slot management module; a slot control module; and a physical slot to management slot contrast table, the slot management module, the slot control module, and the physical slot to management slot contrast table being provided between an input and output control module and a slot interface lower than the input and output control module. The input and output control module accesses the slot interface using virtual slot identification information. The slot management module converts the virtual slot identification information into physical slot identification information while referring to the physical slot to management slot contrast table, and accesses the slot control module corresponding to the physical slot identification information, thereby realizing a physical access of the input and output control module to the slot interface. The slot interface access device is higher in CPU capability than other devices each including the slot interface.

Abstract: A protocol may enable support of the USB 2.0 LPM (Link Power Management) Addendum by a ULPI PHY (Universal Serial Bus Transceiver Macrocell Low-Pin Interface Physical Layer Device), facilitating transmitting the reserved PID (Physical Interface Device) token, used in the LPM Extended Transaction, through a ULPI bus. Bits [3:0] of a ULPI Tx Cmd (Transmit Command) byte may be reused, with the value of those bits being 4?b0 for a transmission (normally indicating a No PID transmission), by configuring the ULPI PHY to qualify the selected four Tx Cmd bits (bits [3:0] of the Tx Cmd) with the Opmode code. The ULPI PHY may thereby interpret bits [3:0] of the Tx Cmd byte based on the value of the Opmode, and may not transmit the Extended PID when the Opmode is set to 2?b10, that is, when the Opmode is indicative of bit-stuffing and NRZI encoding being disabled, for example during a Chirp transmission.

Abstract: A signal generating circuit of a peripheral device for sending a frame information structure (FIS) to a host via a serial transmission channel to change a busy bit representing the state of the peripheral device. The signal generating circuit includes a trigger generator and a signal generator. The trigger generator generates a trigger signal by monitoring a control signal of the signal generating circuit. The signal generator, coupled to the trigger generator, generates the indication according to the trigger signal.

Abstract: An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the data to the host controller integrated circuit in the form of transfer-based transactions.

Abstract: A hypervisor, during device discovery, has code which can examine the south-side management data structure in an adapter's configuration space and determine the type of device which is being configured. The hypervisor may copy the south-side management data structure to a hardware management console (HMC) and the HMC can populate the data structure with south-side data and then pass the structure to the hypervisor to replace the data structure on the adapter. In another embodiment the hypervisor may copy the data structure to the HMC and the HMC can instruct the hypervisor to fill-in the data structure, a virtual function at a time, with south-side management data associations. The administrator can assign south-side data, such as a MAC address for a virtual instance of an Ethernet device, to LPARs sharing the adapter. Thus, a standard way to manage the south-side data of virtual functions is provided.

Abstract: A computer system may include a connecting hub having a plurality of docking regions and be configured to provide to each docking region electrical power, a data network interface, a cooling fluid supply and a cooling fluid return; and a plurality of shipping containers that each enclose a modular computing environment that incrementally adds computing power to the system. Each shipping container may include a) a plurality of processing units coupled to the data network interface, each of which include a microprocessor; b) a heat exchanger configured to remove heat generated by the plurality of processing units by circulating cooling fluid from the supply through the heat exchanger and discharging it into the return; and c) docking members configured to releaseably couple to the connecting hub at one of the docking regions to receive electrical power, connect to the data network interface, and receive and discharge cooling fluid.

Abstract: A method for interrupt priority encoding and vectoring begins with reading pending interrupt bits from an interrupt status register. An entry in a table is located using the pending interrupt bits. The table has a plurality of vector entries for at least one high priority interrupt bit, and a single entry for at least one low priority interrupt bit. A vector address is fetched from the table and a branch is performed to the vector address. An alternate embodiment has high and low priority interrupt vector tables, where the high low priority interrupt vector table is used if no high priority interrupt is present.

Abstract: A support identification device comprising a support (BPA), e.g. a rack or backplane of a telecommunication system, and an identity receiver (PCB), e.g. a printed circuit board or card, coupled to an identity transmitter or connector of the support. The identity transmitter has several read pins (id1-id4=R1-R4) each at a logical level (0, 1) to indicate (identify) the type of support. The card (PCB) further has write terminals (W1, W2) coupled to dynamic terminals (D1, D2) of the support (BPA). These dynamic terminals are coupled to one or more of the read pins (id1-id4). The card is also provided with a program that sets the write terminals at a first logical level, reads a first logical level at each read pin (R1-R4), then sets the write terminals at a second logical level, reads a second logical level at each read pin, and determines from the difference between the first and the second read logical levels to which write terminal each read terminal is coupled, or not.