Abstract: The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract: A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.

Abstract: A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.

Abstract: A Light Emitting Diode (LED) package and a method of manufacturing the same. The LED package includes a substrate. The substrate defines therein a cavity having a tapered shape, a stepped portion formed on the upper end of the cavity, and a through hole formed in the bottom of the cavity. A conductive film fills the through-hole and is formed on the bottom and the side surfaces of the cavity. An LED has a fluorescent layer thereon, and is flip-chip bonded onto the conductive film. An encapsulant encapsulates the cavity. A Zener diode or a rectifier is provided on the silicon substrate.

Abstract: An optoelectronic semiconductor chip includes an active layer with a first and a second major face, including a semiconductor material which emits or receives radiation when the semiconductor chip is in operation; a patterned layer including three-dimensional patterns for outcoupling or incoupling radiation and arranged on the first major face in a beam path of the radiation, wherein the patterned layer includes an inorganic-organic hybrid material.

Abstract: A method for manufacturing an SMT LED device includes steps: providing an LED with two solder slugs extending downwardly from a bottom thereof; providing a circuit board with two first solder pads spaced from each other thereon, the first solder pads each defining a positioning hole therein corresponding to a position of each of the two solder slugs, forming a pair of second solder pads on the circuit board by directly and physically contacting with the circuit board; putting the solder slugs into the positioning holes; subjecting the circuit board and the LED to a reflow soldering, during which the solder slugs are first melted and then solidified to electrically and mechanically connect with the first and second solder pads thereby connecting the LED and the circuit board together.

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

Abstract: Disclosed herein is a high efficiency light emitting diode. The light emitting diode includes: a semiconductor stack positioned over a support substrate; a reflective metal layer positioned between the support substrate and the semiconductor stack to ohmic-contact a p-type compound semiconductor layer of the semiconductor stack and having a groove exposing the semiconductor stack; a first electrode pad positioned on an n-type compound semiconductor layer of the semiconductor stack; an electrode extension extending from the first electrode pad and positioned over the groove region; and an upper insulating layer interposed between the first electrode pad and the semiconductor stack. In addition, the n-type compound semiconductor layer includes an n-type contact layer, and the n-type contact layer has a Si doping concentration of 5 to 7×1018/cm3 and a thickness in the range of 5 to 10 um.

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

Abstract: An active matrix LED display apparatus and a fabrication method thereof are provided. The active matrix LED display apparatus enables to miniaturize pixel by a formation of wiring on bottom layer and an assembly of each block through each eutectic layer into each transistor block receptor and/or each LED block receptor formed according to each color element unit, and to be embodied with high luminance, low power consumption, high reliability and superior optical property by assembling a transistor block having high electron mobility. And the fabricating method of the present invention enables to make efficiently an AM-LED display apparatus at room temperature in a short time by using different shapes of receptor and block depending on the function of a transistor and/or on the color of an LED.

Abstract: The present disclosure provides a repairing method, a repairing structure and a repairing system for a disconnected defect, the repairing method includes: forming a first repairing line connecting two ends of a disconnected portion of a scanning line; forming an insulation layer covering the first repairing line; and forming a second repairing line connecting two ends of a disconnected portion of a data line with the insulation layer located at an intersection of the first repairing line and the second repairing line. By forming the insulation layer between the first repairing line and the second repairing line, the present disclosure avoids the short circuit generated after the scanning line and the data line are repaired, repairs the disconnected defect at the intersection of two metal layers, improves the yield rate of the repairing of the disconnected defect, and reduces manufacturing cost.

Abstract: A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110) with a MEMS mechanical element (111) of a first height (111a) assembled on the pad and connected to the terminals by wires (120) with an insulating coat (121); a ridge (130) on the substrate, which surrounds the MEMS element (111) with a second height (130c) greater than the first height and comprises a plastic compound (131) filled with particles (132) and a surface (130a, 130b) having an adhering moisture-impermeable seal layer (133); and a moisture-impervious lid (140) attached to the ridge by moisture-proof bonds (150, 151), sealing the volume (160) enclosed by the lid, the chip, and the metalized ridge as a hermetic space for the MEMS element (111).

Abstract: A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: An organic light emitting display panel with improved efficiency and lifespan and a method of manufacturing the same are disclosed. The organic light emitting display panel according to the present invention includes a substrate having red, green, blue, and white sub-pixel regions, red, green, and blue color filters respectively formed in the red, green, and blue sub-pixel regions, an overcoat layer that is formed in the red and green sub-pixel regions except for the blue and white sub-pixel regions or is formed in the sub-pixel regions such that a thickness of the overcoat layer in the red and green sub-pixel regions is greater than a thickness of the overcoat layer in the blue and white sub-pixel regions; and organic emitting cells respectively formed in the red, green, blue, and white sub-pixel regions.