Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

Abstract: Method for removing and/or redistributing material in the trenches and/or vias of integrated circuit interconnect structures by a gas cluster ion beam (GCIB) is described to improve the fabrication process and quality of metal interconnects in an integrated circuit. The process entails opening up an undesired ‘necked in’ region at the entrance to the structure, re-depositing the barrier metal from thicker areas such as the neck or bottom of the structure to the side walls and/or removing some of the excess and undesired material on the bottom of the structure by sputtering. The GCIB process may be applied after the barrier metal deposition and before the copper seed layer/copper electroplating or the process may be applied after the formation of the copper seed layer and before electroplating. The method may extend the usability of the known interconnect deposition technologies to next generation integrated circuits and beyond.

Abstract: A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having a plurality of recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the plurality of recesses so that the die face is adjacent the facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extend to the plurality of recesses and the conductive bumps disposed therein. Dielectric filler material may then be introduced through the one or more openings to the recesses and, optionally, between the semiconductor die and interposer substrate.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A TFT array substrate includes a substrate, first–third semiconductor layers, a gate insulating layer, a storage electrode, and a passivation layer. The gate insulating layer separates the first and second semiconductor layers and separates the second and third semiconductor layers. The storage electrode is positioned above the gate insulating layer. A passivation layer encloses the top and side surfaces of the storage electrode. The storage layer and source/drain regions of the first semiconductor layer are doped at the same time.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a sunken section in an insulating film formed on a substrate and forming a barrier metal film on the insulating film inclusive of the sunken section. The method also includes forming a copper-based film over the entire surface so as to fill up the sunken section and forming a copper-based metal interconnection. The interconnection is formed by polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water. A content ratio of the amino acid to the triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.

Abstract: A technique for obtaining light emitting devices manufactured with high yield is provided. The width of a seal pattern (605b) can be kept thin by manufacturing a light emitting device using a second substrate (600a) which has a concave portion (607a) and a concave portion (608a). It therefore becomes possible to make the light emitting device have a narrow frame. In addition, the light emitting device with the narrow frame can be realized by a manufacturing method thereof in which a portion of the second substrate from the concave portion to an edge surface is cut.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure tin on the nickel layer, selectively covering areas of the leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said Leadframe intended for bonding wire attachment.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: A process for fabricating an integrated electrical circuit comprises the formation and then the removal of conducting inserts. Components of the electrical circuit are incorporated into insulating materials superposed on top of a substrate. The process makes it possible to provide an exclusion volume around certain components sensitive to electrostatic coupling, while giving each insulating material a planar surface at the end of a polishing step.

Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

Abstract: A thin film transistor is provided including a transparent insulating substrate, a lower light shielding film disposed above the transparent insulating substrate, a base interlayer film disposed above the lower light shielding film, a semiconductor film disposed above the base interlayer film, wherein the semiconductor film is formed of polycrystalline silicon. A thin film transistor further comprises roughness formed at an interface between the base interlayer and the semiconductor film, a gate insulating film above the semiconductor film, and a gate electrode above the gate insulating film.

Abstract: A method and apparatus for building a memory module using improved patching schemes comprises, mounting multiple primary and secondary memory parts on a multi-layer circuit board, positioning I/O bit line patching networks adjacent to the primary and secondary memory parts, matching read/write control signals for primary and secondary memory parts which share I/O bit line patching networks, testing primary and secondary memory parts to identify non-operable I/O lines, and patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part. The method and apparatus include multi-layer circuit boards which utilize 2-to-1, 4-to-1, and 8-to-1 patching configurations.

Abstract: A method of fabricating a thin film transistor (TFT) array involves ion replacement by oxidation-reduction processes for implementing the metal wiring layout of TFT-LCDs. This can overcome metal etching difficulties and achieve automatic alignment. The method of the invention replaces traditional lithographic etching techniciues.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at least two adhering areas in the direction in which the adhesive tape is peeled. The porous member adheres to the semiconductor wafer by suction and fixes the wafer in place.

Abstract: The invention is used in the field of materials engineering and relates to a method for defining reference magnetizations which could be used, for example, in magnetic sensor technology components. The object of the present invention is to disclose a method for defining reference magnetizations in layer systems, whereby the reference directions can be selected as desired with regard to number and spatial direction. The object is attained through a method for defining reference magnetizations in layer systems in which at least one layer system is produced by geometrically structuring a hard-magnetic and/or soft-magnetic layer and by applying the hard-magnetic and/or soft magnetic layer to at least one antiferromagnetic layer before, during or after a single-stage or multi-stage thermal treatment, whereby the temperature is increased at least to a temperature greater than the coupling temperature and the layer system is cooled afterwards.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.