Abstract: Provided is a method for fabricating an organic semiconductor transistor having an organic polymeric gate insulating layer. The method includes forming an organic gate insulating layer on a substrate by a vapor deposition method using organic monomer sources, and causing a polymerization reaction to occur in the organic gate insulating layer to complete an organic polymeric gate insulating layer. Since the vapor deposition method, which is a low-temperature dry-type technique, is employed, the organic polymeric gate insulating layer can be uniformly formed on a large-area substrate by a simplified in-situ process.

Abstract: An electronic package is provided having a connector and a solder joint that is less susceptible to thermal fatigue. The package includes a die including a first electrically conductive connecting surface having a first coefficient of thermal expansion and a substrate including electrical circuitry and a second electrically conductive connecting surface having a second coefficient of thermal expansion. The package further includes a solder joint connecting the first connecting surface to the second connecting surface. One of the first and second connecting surfaces includes a plurality of pads spaced from each other. By employing an electrical connection having a plurality of pads spaced from each other, the solder joint is relieved to reduce fatigue caused by thermal cycling.

Abstract: A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Abstract: Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

Abstract: Certain methods of the invention permit spacerless manufacture of stacked microelectronic devices by mechanically supporting a second microelectronic component with a wire coating. This wire coating may be sufficiently adhesive to also mechanically bond the second microelectronic component to a first microelectronic component. Other embodiments of the invention provide spacerless stacked microelectronic devices wherein a second microelectronic component is mechanically supported by a wire coating.

Abstract: A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.

Abstract: A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

Abstract: A packaging substrate without plating bar and a method of forming the same is provided. A substrate is firstly provided with circuit patterns formed thereon. Then, solder masks are formed to define connecting points on the circuit patterns. Afterward, the openings of the solder mask on a bottom surface of the substrate are filled with solder material. Thereafter, a seed layer is formed on the bottom surface of the solder mask and the solder material, and then a passivation layer is formed on a surface of the seed layer. Finally, a plating process is carried out by using the seed layer to input cathode electric level to form metal pads on the defined connecting points on the upper surface of the substrate.

Abstract: There is provided a method for manufacturing a silicon wafer or a silicon epitaxial wafer capable of imparting an excellent IG capability thereto in a stable manner by simultaneously realizing higher density of oxide precipitates and larger sizes thereof at a stage prior to a device fabrication process. The present invention is a method for manufacturing a silicon wafer wherein the silicon wafer is subjected to heat treatment to impart a gettering capability thereto comprising at least the following three steps of: a temperature raising step A for generating oxygen precipitation nuclei; a temperature raising step B for growing the oxygen precipitation nuclei; and a constant temperature keeping step C for growing the oxygen precipitation nuclei into oxide precipitates of larger sizes.

Abstract: The invention relates to a process of assembly of at least two silicon substrates. The method comprises: a step of placing in contact a first silicon substrate (9) with a second silicon substrate (10), the first and second substrates (9, 10) being substantially non-transparent for a wavelength ? of laser radiation (R), and a step of illuminating the first silicon substrate (9) with a laser beam of wavelength ? to create a fusion path (21), along the laser beam axis (A1-A2), in the thickness of the first substrate (9) and in all or part of the thickness of the second substrate (10). The invention is applied to the sealing of cavities and of mechanical or electrical joints situated at the interface of two silicon substrates.

Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.

Abstract: An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization is plated on back side of the CVDD wafer. The CVDD wafer is reflowed to flatten the back side.

Abstract: The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

Abstract: Some embodiments of the invention cover the top of a flip chip IC with a conductive adhesive material. This material is used in place of a shielding metal can or plate in some embodiments, while it is used in conjunction with such metal can or plate in other embodiments of the invention. Also, some embodiments use a printing technique to coat the top of the flip chip with the conductive adhesive material. In some embodiments, the coating material is a silver paste.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: Process for fabricating semiconductor components, and semiconductor component, in which a support plate comprises, at various locations, portions provided with respective electrical connection means having electrical connection regions on a front face and having through-holes located in proximity or adjacently to the portions. An integrated-circuit chip is fastened to the front face of each portion of the support plate by means of electrical connection balls. On one side, the electrical connection balls are connected to electrical connection regions of the front face of this plate and, on the other side, to electrical connection pads on the rear face of this integrated-circuit chip, in positions such that one edge of the rear face of each integrated-circuit chip faces at least one through-hole. A curable liquid fill material is delivered in the through-holes so as to at least partly fills a space defined between this support plate and each integrated-circuit chip, respectively.

Abstract: A stress-compensation layer is formed by pressing a solder bump into a compressible film within a mold chase. The stress-compensation layer flows against the solder bump and the compressible film such that at least a portion of the solder ball is embedded in the stress-compensation layer. The compressible film is removed to reveal at least a portion of the solder bump exposed and free of the stress-compensation layer. An article that exhibits a stress-compensation layer with a surface characteristic of the imposed flexible film is also included. A computing system that includes a stress-compensation layer with a surface characteristic of the imposed flexible film is also included.

Abstract: A semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to the at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.

Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.

Abstract: In the process of fabricating an SOI wafer based on the Smart Cut® Process, a stack 34 of an SOI wafer 39 and a residual wafer 38 are separated into the individual wafers using a wafer separation jig 1 of this invention. The wafer separation jig 1 comprises a supporting plane 1p on which the stack 34 is supported in the thickness-wise direction, and a stepped portion 2 disposed on the supporting plane 1p, and having a height adjusted so as to stop movement-by-sliding of the lower wafer of the stack, but so as to allow movement-by-sliding of the upper wafer relative to the lower wafer. Both wafers are separated from each other by inclining the supporting plane 1p with the stack 34 placed thereon, so as to allow the upper wafer to move by sliding as being driven by its own weight in the in-plane direction relative to the lower wafer. This method is successful in effectively suppressing friction between the wafers, and thus in preventing the wafer surface from being scratched.