Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

Abstract: A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting the first and second cavities. The first cavity is adapted to enclose the integrated circuit chip on the substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.

Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.

Abstract: Consistent with an example embodiment, there is a method for manufacturing a semiconductor device. The semiconductor device comprises a semiconductor body provided at a surface with a non-volatile memory including a memory cell with a gate structure with an access gate and a gate structure with a control gate and a charge storage region situated between the control gate and the semiconductor body. In the method, on the surface of the semiconductor body a first one of said gate structures is formed with side walls extending substantially perpendicular to the surface, a conductive layer is deposited on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining only a first one of the side walls of the first gate structure.

Abstract: Disclosed is a fabrication process of a highly reliable semiconductor device formed by stacking and pattering a polycrystalline silicon film, a tungsten nitride film and a tungsten film over a gate insulator film on a semiconductor substrate, thereby forming gate electrodes. Then, a conductive plasma processing is performed using an ammonia gas at a temperature for the semiconductor substrate of 500° C. or lower, thereby nitriding the side wall for the gate electrode to form a nitride film, and then conducting plasma processing by using an oxygen gas in a state at a temperature for the semiconductor substrate of 500° C. or lower thereby restoring damages or defects in the silicon oxide film present in the surface portion of the semiconductor substrate at the periphery of the gate electrode.

Abstract: A method for monitoring the quality of a manufacturing process for making detector panels that have a plurality of pixels in a two-dimensional array includes, in each detector panel, manufacturing a set of baseline pixels and a set of test pixels. Each test pixel has an electrical component having a geometric dimension varied by an amount sufficient to introduce a measurable variation in a test that measures parameters of pixels that are dependent upon the varied dimension. The method further includes performing the test on the set of baseline pixels and the set of varied pixels, analyzing the results of the test, and adjusting parameters of the manufacturing process in accordance with the analysis.

Abstract: Method of forming a lightly phosphorous doped silicon film. A substrate is provided. A process gas comprising a phosphorous source gas and a disilane gas is used to form a lightly phosphorous doped silicon film on the substrate. The diluted phosphorous source gas has a phosphorous concentration of 1%. The phosphorous source gas and the disilane gas have a flow ratio less than 1:100. The lightly phosphorous doped silicon film has a phosphorous doping concentration less than 1×1020 atoms/cm3.

Abstract: Embodiments of the present invention include first and second substrate structures with underfill injected into a substrate structure interface through a feature of the substrate structure, a heat spreader, and the like.

Abstract: A method of constructing a microelectronic assembly as provided. A mold piece is locating over a microelectronic die carrying an integrated circuit. An encapsulant is injected into a space defined between surfaces of the mold piece and the microelectronic die. The encapsulant includes a liquid phase epoxy and a solid phase catalyst compound when injected. The encapsulant mixture is heated in the space to a temperature where the catalyst compound becomes a liquid and cures the epoxy. The catalyst compound may, for example, be polystyrene and the catalyst may be diphenyl phosphine. The catalyst compound is then heated to above its glass transition temperature so that the diphenyl phosphine is released from the polystyrene. The diphenyl phosphine then cures the epoxy. The epoxy is preferably a liquid at room temperature.

Abstract: A system for providing electrical contacts between a die and an electrical device includes a package having a first major surface, a second major surface, a first scalloped edge, a second scalloped edge, and a solid end adapted for insertion into a slot. The solid end for carries power to the die or input/output signals. The scalloped edges also carry power. The package includes a plurality of electrical pins which carry input/output signals as well as power. The socket of the system includes a base having an opening therein adapted to receive the package. A cover with openings for receiving the pins covers the base. A power contact unit includes a pair of scalloped edges and a slot. The power contact unit and the cover moves with respect to the base of the socket.

Abstract: In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.

Abstract: In the process of plasma dicing in which the semiconductor wafer 6 is divided into individual pieces by plasma, SiO2 layer 42 and the protective layer 43, which are formed covering the active layer 41, are utilized as an etching stop layer for absorbing fluctuation of the etching rate in the first plasma dicing step in which the wafer base layer 40 is etched and cut off. Next, the second plasma dicing step is conducted in which the etching stop layer exposed by the first plasma dicing step is cut off with plasma of the second plasma generating gas capable of etching at a high etching rate, and heat damage is prevented which is caused when the protective sheet 30 is exposed to plasma for a long period of time.

Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, four bar leads connected to the suspending leads and arranged outside the semiconductor chip, first wires for connecting pads of the semiconductor chip and the leads, second wires for connecting the pads of the semiconductor chip and the bar leads, and a sealing body for sealing the semiconductor chip using resin. On a back surface of the sealing body, a distance between the suspending lead exposing portion and the lead exposing portion is set to a value equal to or more than a distance between the lead exposing portions.

Abstract: A gate insulator film and a gate electrode are formed on a semiconductor substrate, and then a layered stack of a SiO2 film and a SiN film is formed on the entire surface. Subsequently, sidewalls made of polysilicon film are formed adjacent to the gate electrode via the layered stack of the SiO2 film and the SiN film. Then, using as a mask the gate electrode, portions of the layered stack adjacent to the gate electrode, and the sidewalls, an ion dopant is implanted into a device active region to thereby form source/drains therein, and the sidewalls are then removed. At this stage, since the gate insulator film is completely covered with the layered stack, the gate insulator film is not ablated or retreated even on a device isolation insulator film.

Abstract: An object of the invention is to reduce the manufacturing cost of EL display devices and electronic devices incorporating the EL display devices. An EL material is formed by printing in an active matrix EL display device. Relief printing or screen printing may be used as the method of printing. Manufacturing steps of the EL layer is therefore simplified and reduction of manufacturing cost is devised.

Abstract: A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting said first and second cavities. The first cavity is adapted to enclose said integrated circuit chip on said substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.

Abstract: There is disclosed a flip-chip-type method of assembling semiconductor devices. A one-step encapsulation process promotes adhesion of the die to the lead fingers and prevents the potential of shorts developing between the adjacent bumps or lead fingers. Conventional mold compound is used to reduce localized stress caused by coefficient of thermal expansion (CTE) mismatch between the die and substrate, or the lead frame.

Abstract: A semiconductor device having area array bump electrodes suitable for flip chip packaging is disclosed. A semiconductor chip with wire bonding electrodes arranged along peripheral edges thereof is provided, then gold wire bump electrodes are formed over the wire bonding electrodes, and thereafter a wiring tape substrate is superimposed on the semiconductor chip and is bonded thereto with an adhesive. On a back surface of the wiring tape substrate are formed wiring connections correspondingly to the electrodes. Further, at the time of bonding with use of the adhesive, convex tips of the gold wire bump electrodes formed respectively on the electrodes of the semiconductor chip pierce through the adhesive to connect the gold wire bump electrodes and the connections electrically with each other. On a surface of the wiring tape substrate are formed area array bump electrodes, whose pitch is larger than the pitch of the electrodes formed on the semiconductor chip.

Abstract: A method of bonding multiple layers is provided. The method includes the steps of stacking the multiple layers on top of each other and volumetrically heating the stack of multiple layers to a predetermined temperature. It is preferred that the stack is heated by electromagnetic induction.