Abstract: A semiconductor integrated circuit device includes a semiconductor substrate having a first surface and including an electrode on the first surface of the semiconductor substrate; a surface protecting film covering the first surface of the semiconductor substrate; an electrode underlayer on the surface protecting film, in electrical contact with the electrode; an external electrode on the surface protecting film, in electrical contact with the electrode underlayer, and having a substantially planar external surface; and a barrier part on the surface protecting a barrier against intrusion of moisture and ions into the semiconductor substrate, the barrier part having the same area as the semiconductor substrate and a substantially planar external surface.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: Device modules with pins and methods for making device modules with pins are disclosed. One embodiment is directed to a method including forming a polymeric circuit structure having a first side and a second side on a substrate. The formed first side is adjacent to the substrate. A pin is bonded to the second side of the polymeric circuit structure. At least a portion of the substrate is removed to expose at least a portion of the first side of the polymeric circuit structure, and a device is mounted on the first side of the polymeric circuit structure.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: A method for reducing soft error rates in semiconductor devices includes adding an isotopically enriched 11B compound during the manufacture of a semiconductor device. Such isotopically enriched 11B compounds include orthoborates (BOR3), acyl borates (B(OCOR)3), peroxo borates (OOR)3, boronic acids (RB(OH)2), boron halides, boron hydrides, inorganic boranes, amine boranes, aminoboranes, carboranes, and borazines, where R is an alkyl group. Disclosed uses include adding between 1% to 100% of the isotopically enriched 11B compound to an underfill material in flip-chip assembly; adding between 1% to 100% of the isotopically enriched 11B compound to an encapsulent; and adding between 1% to 100% of the isotopically enriched 11B compound to an adhesive.

Abstract: A method for manufacturing a chip scale package (CSP) including a semiconductor chip and conductive bumps is disclosed. In the present invention, a flexible substrate is provided with a conductive pattern formed thereon. The substrate has a top surface and a bottom surface. Then, a first photosensitive resin pattern is formed over the top surface of the substrate. Next, the first photosensitive resin pattern is cured. Subsequently, a second photosensitive resin pattern is formed over the cured first photosensitive resin pattern. The second photosensitive resin pattern includes a slit comprising a bottom of the first photosensitive resin pattern and side walls of the second photosensitive resin pattern. With the present invention, the problem of burning of neighboring patterns as well as the problem of the overflow of the encapsulant can be overcome.

Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: A small size electronic part comprises a silicon substrate having a functional element and a signal output portion to output a signal from the functional element to outside the electronic part; a glass substrate provided on the silicon substrate such that the signal output portion of the silicon substrate is in contact with the glass substrate; a communicating hole provided in the glass substrate and at least a portion of the signal output portion of the silicon substrate so as to pass through the glass substrate and cut into at least a part of the signal output portion; and a conductive film provided on an inner wall surface of the communicating hole and extending on a surface of the glass substrate.

Abstract: The present invention relates to a semiconductor package and a fabricating method thereof, more particularly, to a chip size package of a wafer level and a fabricating method thereof. Accordingly, the present invention eases sufficiently the thermal stress generated from the difference of heat expansion rates between the semiconductor chip and the PCB substrate, increases the reliance of the wires as the stress on the wires are greatly reduced, simplifies the fabrication process, and reduces the product cost owing to simplified processes as equipments for metal deposition, metal plating and etch arc not necessary. The present invention, as embodied and broadly described, the present invention includes a semiconductor chip, a chip pad in a first area of the semiconductor chip, a stress-easing layer formed in a second area of the semiconductor chip, a conductive wire connecting the chip pad to the stress-easing layer, and an electrical conductor on the conductive wire over the stress-easing layer.

Abstract: Die bonding equipment for fine pitch ball grid array package includes: a semiconductor chip pickup stage for inspecting a status of a loaded semiconductor chip and a corresponding position thereof; an alignment stage on which the semiconductor chip fixed on a mount head is aligned; a chip transfer unit for transferring the semiconductor chip from the semiconductor chip pickup stage to the alignment stage; a guide rail for guiding a mount tape frame; a status inspecting unit disposed at a selected position over the guide rail, for inspecting a status and a position of the land pattern on the mount tape frame; and a bonding unit for bonding the land pattern to the semiconductor chip which is mounted on the mount head. The equipment only bonds semiconductor chips (good or defective) to lands patterns having the same status (good or defective).

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: A chip carrier and lid are sealed by mounting the chip carrier in an inverted position and mounting a lid having a sealing preform in an inverted position beneath and facing the chip carrier. The chip carrier and lid are then heated to melt the sealing preform and the chip carrier and lid are moved together to join them at the sealing preform.