Abstract: Methods and systems of protecting substrates that are intended for use in fluidic devices are described. In accordance with one embodiment, sealant material is applied over one or more edges of at least one multi-chip module substrate that is intended for use in a fluidic device. At least one edge has an exposed electrical interconnect and the sealant material is applied over less than an entirety of the substrate and sufficiently to cover the exposed electrical interconnect. The sealant material is exposed to conditions effective to seal the one or more edges.

Abstract: Methods of bulk manufacturing high temperature sensor sub-assembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.

Abstract: Passivating layers methods for forming the same are provided for packaged integrated circuit devices. In particular, an integrated circuit die is mounted in a plastic leaded chip carrier, and a photosensitive material is then deposited over the surfaces to be passivated. Portions of the photosensitive material are then exposed to UV light, resulting in a crosslinked siloxane network. In this way, a low-temperature photodefinable passivation layer is provided for the package, with characteristics similar to conventional oxides. Advantageously, the photosensitive material can be patterned during the UV exposure, and unexposed portions selectively removed to leave the passivation layer only over desired portions of the package.

Abstract: A silicide film is selectively formed at least on diffusion layers of a MOS transistor. In the method for forming the silicide film includes, a first metal film is selectively formed at least on diffusion layers. A first annealing is applied to allow at least the diffusion layers to react with the first metal film. A part of the sidewalls is removed to form a gap with reacted film of the first metal film. A second annealing is performed at a temperature higher than that of the first annealing to form a reacted film. This makes it possible to form a silicide film having preferable electric characteristics on a gate and diffusion layers being fine in dimension and high in impurity concentration, in a self-aligning fashion without producing “bite of silicide.

Abstract: A semiconductor package and the leadframe therefor having a reverse-down set part formed in the tie bar supporting the chip paddle. The reverse-down set part of the tie bar may be formed by a mechanical stamping process in such a way that it is present within the insulating body, interlocking therewith. This feature also facilitates the prevention of a short circuit between the tie bar that is exposed externally from the package body and the exposed internal lead through solder upon the mounting of a semiconductor package onto a motherboard.

Abstract: A package structure and method for a card comprises respective attachment of first and second conductive covers each having a vertical piece extending on one side thereof with first lateral surface of first and second plastic frames in use of a low temperature adhesive therebetween to form first and second half cases, and combination of the first and second half cases with insertion of another adhesive or sonic welding between second lateral surfaces of the first and second plastic frames. The plastic frame also has an outer surface formed with a recess to accommodate the vertical piece of the conductive cover and an adhesive area on the first lateral surface formed deep into the plastic frame to be coated with the low temperature adhesive in order for the attachment of the conductive cover.

Abstract: A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e. solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.

Abstract: Glass, for encapsulating a semiconductor, which is substantially free of lead or other harmful ingredients, but which exhibits a sealing temperature of not higher than 710° C., and which stably seals with Dumet. Further, when the glass has a viscosity of 106 dPa·s, the temperature of said glass is not higher than 710° C., and includes two or more of Li2O, Na2O and K2O and B2O3. Also, the glass may comprise: SiO2, B2O3 and Al2O3 in an amount of from 40 to 70%, from 5 to 20% and from 0 to 15% by weight, respectively; MgO, CaO, SrO, BaO and ZnO in a total amount of from 0 to 45% by weight; and Li2O, Na2O and K2O in a total amount of from 5 to 25% by weight.

Abstract: In order to mount a semiconductor chip on a carrier layer, consolidated filler material is applied between the semiconductor chip and the carrier layer. The filler material is sucked, under the application of a partial vacuum, from at least one edge section of the semiconductor chip to at least one other edge section of the semiconductor chip. As a result, a package is provided in which the filler material is essentially free of air inclusions.

Abstract: A method of encapsulating a circuit assembly including a chip; a substrate; at least one solder joint which spans between the chip and the substrate forming an electrically conductive connection between the chip and the substrate by applying an encapsulant adjacent the solder joint, wherein the encapsulant comprises a thermoplastic polymer formed by ring opening polymerization of a cyclic oligomer.

Abstract: A chip scale surface-mountable packaging method for electronic and micro-electro mechanical system (MEMS) devices is provided. The chip scale surface-mountable packaging method includes: (a) forming an interconnection and sealing pattern as a deep trench in one surface of a conductive cover substrate using semiconductor fabricating and micromachining techniques; (b) filling the trench as the pattern of the cover substrate with an insulating material such as glass or ceramic, and planarizing the surface of the cover to form a bonding pattern; (c) accurately aligning the cover substrate with a device substrate, in which electronic or MEMS devices are integrated, and bonding the cover substrate and the device substrate; (d) polishing the other surface of the cover substrate and forming an electrode pattern thereon; and (e) dicing the sealed and interconnected substrates to form a complete chip scale package.

Abstract: Some of the members constituting a semiconductor element are formed from &agr;-Si and an HSG forming process is implemented to form hemispherical polysilicon grains at some of the members formed from &agr;-Si. Thus, a semiconductor device that is achieved without requiring a great number of manufacturing steps such as film formation and etching, facilitates control of the individual steps and assures reliable electrical connection between the members and a method of manufacturing such a semiconductor device are provided.

Abstract: An interconnect assembly and a fluxless method for forming the interconnect assembly. The fluxless method includes providing a first semiconductor substrate having a first pad connected thereto. A post is connected to the first pad and includes a length greater than a thickness of the first pad, and a metallic solder disposed on an associated end of the post. A second semiconductor substrate is provided as having a second pad connected thereto. The fluxless method further includes depositing an unfilled polymeric liquid on the second pad, aligning and contacting the metallic solder with the unfilled polymeric liquid, and forcing by pressure the first and second semiconductor substrate toward each while simultaneously heating the metallic solder and the unfilled polymeric liquid to form a metallurgical joint between the second pad and the metallic solder.

Abstract: A magnetoelectronics element (40) is provided that is comprised of a first magnetic layer (42), a first tunnel barrier layer (44) on the first magnetic layer (42), a second magnetic layer (46) on the first tunnel barrier layer (44) and a stressed over-layer (48) on the second magnetic layer (46), which is configured to alter a switching energy barrier of the second magnetic layer (46).

Abstract: A package for connecting an integrated circuit to a printed circuit board. The package includes an interconnect having a deflectable cantilever and a solder bump. When the integrated circuit is affixed to the interconnect, the solder bump deflects the cantilever. When the solder bump is heated such that the solder reflows, the cantilever springs toward its non-deflected position and is at least partially absorbed by the reflowing solder.

Abstract: A method for fabricating a boron-contained silicate glass layers, such as borosilicate and borophosphosilicate glass films at low temperature using High Density Plasma CVD with silane derivatives as a source of silicon, boron and phosphorus compounds as a doping compounds, oxygen is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a flow capability of boron-contained silicate glass materials which provide a film with good film integrity and void-free gap-fill within the steps of device structures after low temperature thermal budget anneal conditions.

Abstract: A three-dimensional semiconductor device includes a cylindrical heat sink, wherein a CPU is provided on a substantially center of an inner bottom surface of the cylindrical heat sink, semiconductor chips are respectively mounted on an outer peripheral surface and an inner peripheral surface of the cylindrical heat sink, and the CPU is connected to an upper heat sink.

Abstract: A flexible substrate strip comprises a plurality of substrate units adapted for mounting semiconductor chips. The surface of the flexible substrate strip is provided with a plurality of degating regions at locations such that the edges of mold runners and gates of a mold used to encapsulate the semiconductor chips in encapsulant material fit entirely within the degating regions when the substrate strip is placed in the mold during encapsulation of the semiconductor chips. The present invention is characterized in that each degating region has a buffer region at a location corresponding to the gate of the mold during encapsulation. The degating regions have a degating region material formed thereon with the buffer regions not coated with the degating region material. The adhesive force between the encapsulant material and the degating region material is less than the adhesive force between the encapsulant material and the substrate.

Abstract: A method for vacuum packaging MEMS devices is provided that comprises forming a plurality of MEMS devices (12) on a device wafer (10). A first sealing ring (16) is formed surrounding one of the MEMS devices (12) and any associated mating pads (70). A plurality of integrated circuit devices (80) is formed on a lid wafer (30) where each integrated circuit device (80) has one or more associated mating pads (82) and one or more associated bonding pads (86). A plurality of second sealing rings (32) is formed on the lid wafer (30) where each of the second sealing rings (32) surrounds one of the integrated circuit devices (80) and any associated bonding pads (82). The second sealing ring (32) is positioned between the perimeter of the integrated circuit device (80) and the associated bonding pads (86). A sealing layer is formed on either each first sealing ring (16) or each second sealing ring (32).