Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: A semiconductor device has a super junction structure and includes a first semiconductor layer of the second conductive type disposed on the first column region and the second column region, a second semiconductor layer of the first conductive type disposed on the first semiconductor layer, a first semiconductor region of the first conductive type that is electrically connected to the first electrode and is disposed in a surface layer portion of the second semiconductor layer to be separated from the first semiconductor layer, and a second semiconductor region of the second conductive type that is electrically connected to the second electrode and that is disposed at least in the surface layer portion of the second semiconductor layer to be separated from the first semiconductor region and is electrically connected to the first semiconductor layer.

Abstract: A memory device, transistor, and methods of making the same, the memory device including a memory device including: a ferroelectric (FE) structure including: a dielectric layer, an FE layer disposed on the dielectric layer, and an interface metal layer disposed on the FE layer, in which the interface metal layer comprises W, Mo, Ru, TaN, or a combination thereof to induce the FE layer to have an orthorhombic phase; and a top electrode layer disposed on the interface metal.

Abstract: A varactor may include a gate electrode; a graphene layer; and a ferroelectric layer between the gate electrode and the graphene layer.

Abstract: Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference.

Abstract: A monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding is provided. In an exemplary aspect, an ETL MMIC according to this disclosure includes a MMIC substrate having an active side, an ETL dielectric layer covering the active side, and a topside ground plane over the ETL dielectric layer. The active side includes one or more transmission lines or other components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in an external circuit assembly. The topside ground plane in the ETL MMIC provides shielding to reduce such electromagnetic coupling. The topside ground plane can also facilitate improved thermal paths for heat dissipation, such as through a redistribution layer (RDL) to a next higher assembly (NHA) and/or through a backside ground plane of the MMIC substrate.

Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.

Abstract: A method of fabricating a semiconductor device is described. A first material layer is formed, wherein the first material layer contains crystalline aluminum nitride or aluminum scandium nitride (AlScN) with a first Sc content. A second material layer is formed on the first material layer, wherein the second material layer contains aluminum scandium nitride (AlScN) with a second Sc content higher than the first Sc content. A third material layer is formed on the second material layer, wherein the third material layer contains aluminum scandium (AlSc).

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A light-emitting device comprising: a first electrode, a second electrode facing the first electrode; an emission layer disposed between the first electrode and the second electrode; and a first charge transport layer disposed between the first electrode and the emission layer, wherein a band gap energy of the emission layer and a band gap energy of the first charge transport layer are different from each other, the emission layer comprises a first perovskite compound, and the first charge transport layer consists of a second perovskite compound.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: A method for bonding a first substrate with a second substrate, with the following sequence: production of a first amorphous layer on the first substrate and/or production of a second amorphous layer on the second substrate, bonding of the first substrate with the second substrate at the amorphous layer or at the amorphous layers to form a substrate stack, irradiation of the amorphous layer or the amorphous layers with radiation in such a way that the amorphous layer or the amorphous layers is/are transformed into a crystalline layer or crystalline layers.

Abstract: An example of a method of micro-transfer printing comprises providing a micro-transfer printable component source wafer, providing a stamp comprising a body and spaced-apart posts, and providing a light source for controllably irradiating each of the posts with light through the body. Each of the posts is contacted to a component to adhere the component thereto. The stamp with the adhered components is removed from the component source wafer. The selected posts are irradiated through the body with the light to detach selected components adhered to selected posts from the selected posts, leaving non-selected components adhered to non-selected posts. In some embodiments, using the stamp, the selected components are adhered to a provided destination substrate. In some embodiments, the selected components are discarded. An example micro-transfer printing system comprises a stamp comprising a body and spaced-apart posts and a light source for selectively irradiating each of the posts with light.

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: A variable reluctance motor load mapping apparatus includes a frame, an interface disposed on the frame configured for mounting a variable reluctance motor, a static load cell mounted to the frame and coupled to the variable reluctance motor, and a controller communicably coupled to the static load cell and the variable reluctance motor, the controller being configured to select at least one motor phase of the variable reluctance motor, energize the at least one motor phase, and receive motor operational data from at least the static load cell for mapping and generating an array of motor operational data look up tables.

Abstract: An oxide semiconductor transistor includes: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer may include a source region and a drain region which are on the insulating substrate outside the trench and are apart from each other with the gate electrode therebetween.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.