Abstract: A transistor device and the manufacturing methods are described. The device includes a gate structure having a gate layer and a ferroelectric layer, source and drain terminals, and a crystalline channel portion. The source and drain terminals are disposed at opposite sides of the gate structure. The crystalline channel portion extends between the source and drain terminals. The source and drain terminals are disposed on the crystalline channel portion and the gate structure is disposed on the crystalline channel portion. The crystalline channel portion includes a first material containing a Group III element and a Group V element, the gate layer includes a second material containing a Group III element and a rare-earth element, and the ferroelectric layer includes a third material containing a Group III element, a rare-earth element and a Group V element.

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

Abstract: A method for manufacturing an IGBT device includes: forming a source of the IGBT device in a substrate, wherein the substrate is an MCZ substrate; performing annealing processing on the substrate, wherein a layer of oxide is formed on the surface of the source during an annealing process; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is comprised of a silicon nitride layer, a first type oxide layer, and a second type oxide layer, and a material used to form the first type oxide layer is different from a material used to form the second type oxide layer; and performing nitrogen annealing processing on the substrate.

Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising Li(Alx1Ga1?x1)O2 wherein 0?x1?1; and a second epitaxial oxide layer comprising (Alx2Ga1?x2)2O3 wherein 0?x2?1.

Abstract: A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer.

Abstract: A monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding is provided. In an exemplary aspect, an ETL MMIC according to this disclosure includes a MMIC substrate having an active side, an ETL dielectric layer covering the active side, and a topside ground plane over the ETL dielectric layer. The active side includes one or more transmission lines or other components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in an external circuit assembly. The topside ground plane in the ETL MMIC provides shielding to reduce such electromagnetic coupling. The topside ground plane can also facilitate improved thermal paths for heat dissipation, such as through a redistribution layer (RDL) to a next higher assembly (NHA) and/or through a backside ground plane of the MMIC substrate.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: The present invention discloses a metal oxide (MO) semiconductor, which is implemented by respectively doping at least an oxide of rare earth element R and an oxide of rare earth element R? into an indium-containing MO semiconductor to form an InxMyRnR?mOz semiconductor. According to the present invention, the extremely high oxygen bond breaking energy in the oxide of rare earth element R is used to effectively control the carrier concentration in the semiconductor, and a charge transportation center can be formed by using the characteristic that the radius of rare earth ions is equivalent to the radius of indium ions, so that the electrical stability of the semiconductor is improved. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.

Abstract: The present invention discloses a metal oxide (MO) semiconductor, which is obtained by doping a small amount of rare-earth oxide (RO) as a photo-induced carrier transportion center into an indium-containing MO semiconductor to form a (In2O3)x(MO)y(RO)z semiconductor material. According to the present invention, a charge transportion center can be formed by utilizing the characteristics that the radius of rare-earth ions is equal to that of indium ions, and 4f orbitals in the rare-earth ions and 5s orbitals of the indium ions, so as to improve the stability under illumination. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate. In some embodiments, the marking pattern also includes a central marking structure that divides the marking area into a first marking sub-area farther from a device area and a second marking sub-area closer to the device area, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

Abstract: The present invention discloses an auxiliary electrode transfer structure and a manufacturing method for a display panel. The auxiliary electrode transfer structure includes a transparent base layer; a light-to-heat transformation layer disposed above the transparent base layer; and an auxiliary electrode disposed above the light-to-heat transformation layer; a laser mechanism configured to form laser, wherein the laser penetrates the transparent base layer to the light-to-heat transformation layer.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: An array substrate (100) includes a first type of electroluminescent diode (110). The first type of electroluminescent diode (110) includes a first electrode (111), alight emitting structure layer (112) comprising nanoparticles (114), and a second electrode (113) disposed in a stacked manner. The nanoparticles (114) may be configured to increase luminous efficiency of the first type of electroluminescent diode (110).

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped