Abstract: The present invention provides a patterned silicon substrate-silicon germanium thin film composite structure comprising a silicon substrate having a patterned structure, a silicon germanium buffer layer positioned on the silicon substrate, a silicon germanium/silicon superlattice layer positioned on the silicon germanium buffer layer and a silicon germanium thin film layer positioned on the silicon germanium/silicon superlattice layer, wherein the silicon germanium/silicon superlattice layer comprises silicon germanium layers and silicon layers which are grown alternately. The present invention also provides a preparation method of the patterned silicon substrate-silicon germanium thin film composite structure of the present invention. The present invention also provides an application of the patterned silicon substrate-silicon germanium thin film composite structure of the present invention in strained silicon devices.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

Abstract: A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N?3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion.

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: A photodetector having a small form factor and having high detection efficiency with respect to both visible light and infrared rays may include a first electrode, a collector layer on the first electrode, a tunnel barrier layer on the collector layer, a graphene layer on the tunnel barrier layer, an emitter layer on the graphene layer, and a second electrode on the emitter layer. The photodetector may be included in an image sensor. An image sensor may include a substrate, an insulating layer on the substrate, and a plurality of photodetectors on the insulating layer. The photodetectors may be aligned with each other in a direction extending parallel or perpendicular to a top surface of the insulating layer. The photodetector may be included in a LiDAR system.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor assembly includes a power semiconductor, a housing containing the power semiconductor, and electrically conductive channels. The electrically conductive channels are arranged to direct coolant through the housing. Heat generated by the power semiconductor can therefore be absorbed by the coolant. The electrically conductive channels are also electrically connected with the power semiconductor to form terminals for the power semiconductor.

Abstract: A transparent display device includes a substrate in which a sub-pixel having an organic light emitting diode and an auxiliary sub-pixel adjacent to the sub-pixel and having an auxiliary organic light emitting diode are placed, wherein the organic light emitting diode includes a 1-1 electrode in which a transparent conductive layer and a reflective layer are laminated, and the auxiliary organic light emitting diode includes a 1-2 electrode in which the transparent conductive layer is extended and provided.

Abstract: The present application discloses an oxide semiconductor thin-film and a thin-film transistor consisted thereof. The oxide semiconductor thin-film is fabricated by doping a certain amount of rare-earth oxide (RO) as light stabilizer to metal oxide (MO) semiconductor. The thin-film transistor comprising a gate electrode, a channel layer consisted by the oxide semiconductor thin-film, a source and drain electrode; the thin-film transistor employing etch-stop structure, a back-channel etch structure or a top-gate self-alignment structure.

Abstract: Ferroelectric semiconductor device with a memory cell, with a ferroelectric memory layer and a first conductive layer disposed on the ferroelectric memory layer; and a semiconductor device connected to the memory cell. The ferroelectric memory layer of the memory cell can include a mixed crystal with a group III nitride and a non-group III element.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.