Abstract: In a method of manufacturing a semiconductor device, a first source/drain structure is formed over a substrate, one or more first insulating layers are formed over the first source/drain structure, a first opening is formed in the one or more first insulating layers, the first opening is filled with a first conductive material to form a first lower contact in contact with the first source/drain structure, one or more second insulating layers are formed over the first lower contact, a second opening is formed in the one or more second insulating layers to at least partially expose the first lower contact, a first liner layer is formed on at least a part of an inner side face of the second opening, and the second opening is filled with a second conductive material to form a first upper contact in contact with the first lower contact without the first liner layer.

Abstract: Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a memory region and a logic region, the memory region including a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets includes: a first semiconductor nanosheet, a second group of nanosheets vertically arranged over a second region of the substrate adjacent to the first region, wherein the second group of nanosheets includes: a second semiconductor nanosheet, and a third semiconductor nanosheet over the second semiconductor nanosheet, a first metal gate layer surrounding the first semiconductor nanosheet, and a second metal gate layer surrounding the second semiconductor nanosheet, wherein the first metal gate layer is in direct contact with the second metal gate layer.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: A bonded wafer includes: a first wafer having a first surface and a second surface opposite to the first surface, and including a functional element on the first surface; and a second wafer in which a structure having at least one of a hole, a groove and a cavity is formed; wherein an annular protrusion is formed to have a shape to extend along an outer periphery on the second surface of the first wafer; wherein at least a portion of the second wafer is a reduced-diameter portion having a diameter smaller than an inner diameter of the annular protrusion; and wherein, under a state in which the reduced-diameter portion is fitted into a region surrounded by the annular protrusion of the first wafer, the second wafer is bonded to the second surface at least at the region.

Abstract: A device that detects fluid flow may include a housing member that couples to a conduit and an apparatus that outputs the fluid. The device may also include a flow mechanism that detects the fluid flow through the conduit and the apparatus and a transmitter that transmits a signal indicative of the fluid flow to a computing device.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers above the substrate. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area. The 3D memory device further includes first channel structures each extending vertically through the first area of the memory stack and including a drain at its upper end, and second channel structures each extending vertically through the second area of the memory stack and including a source at its upper end. The 3D memory device further includes semiconductor connections disposed vertically between the substrate and the memory stack.

Abstract: Systems, apparatuses, and methods related to reduction of crystal growth resulting from annealing a conductive material are described. An example apparatus includes a conductive material selected to have an electrical resistance that is reduced as a result of annealing. A stabilizing material may be formed over a surface of the conductive material. The stabilizing material may be selected to have properties that include stabilization of the reduced electrical resistance of the conductive material and reduction of a degree of freedom of crystal growth relative to the surface resulting from recrystallization of the conductive material during the annealing.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

Abstract: A photoelectric conversion device, including: a photoelectric conversion substrate having a plurality of photoelectric conversion portions and a microlens array arranged on the plurality of photoelectric conversion portions; a light-transmitting plate covering the microlens array; and a film arranged between the microlens array and the light-transmitting plate, wherein the film has a refractive index within a range from 1.05 to 1.15, an average transmittance of light in a wavelength region within a range from 400 nm to 700 nm of 98.5% or higher, and a film thickness within a range from 500 nm to 5000 nm.

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Abstract: The light-emitting device includes a light-emitting element, a light-transmissive member, a light-blocking layer and a light-reflective member. The light-transmissive member has a first main surface and a second main surface opposite to each other. The first main surface and the second main surface are smaller than a light-emitting surface of the light-emitting element. The first main surface faces the light-emitting surface of the light-emitting element. The light-blocking layer is disposed on the light-emitting surface to cover a region between an outer edge of the light-emitting surface and an outer edge of the first main surface. The light-reflective member covers at least a portion of lateral surfaces of the light-emitting element and at least a portion of the light-transmissive member. The light-blocking layer extends inward of the outer edge of the first main surface.

Abstract: A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

Abstract: The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements.

Abstract: A coating liquid for forming an oxide or oxynitride insulator film, the coating liquid including: A element; at least one selected from the group consisting of B element and C element; and a solvent, wherein the A element is at least one selected from the group consisting of Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B element is at least one selected from the group consisting of Ga, Ti, Zr, and Hf, the C element is at least one selected from the group consisting of Group 2 elements in a periodic table, and the solvent includes at least one selected from the group consisting of an organic solvent having a flash point of 21° C. or more but less than 200° C. and water.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a plurality of ring-shaped regions, and a semi-insulating layer. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region surrounds the second semiconductor region, and is provided on the first semiconductor region. The ring-shaped regions surround the second semiconductor region. The second electrode is provided on the second semiconductor region. The third electrode is provided on the third semiconductor region. The semi-insulating layer contacts the first semiconductor region, the second electrode, the ring-shaped regions, and the third electrode. The ring-shaped regions include first and second ring-shaped regions provided between the first ring-shaped region and the third semiconductor region.

Abstract: A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773° C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as tI, and a thickness of each of the metal layers being denoted as tM, a value of tI/tM is greater than or equal to 4.3.

Abstract: A light emitting diode includes an n-type confinement layer, a quantum well active layer formed on the n-type confinement layer, a p-type confinement layer formed on the quantum well active layer, a gallium phosphide-based quantum dot structure formed in the p-type confinement layer, and a GaP-based current spreading layer formed on the GaP-based quantum dot structure. A method of manufacturing the light emitting diode is also provided.

Abstract: In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner.