Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

Abstract: A ferroelectric field effect transistor includes a semiconductor substrate that contains a semiconductor channel that extends between a source region and a drain region. A ferroelectric gate dielectric layer is disposed over the semiconductor channel, and includes a ferroelectric material having a charge trapping band including electronic states generated by interfacial traps of the ferroelectric material. A gate electrode is located on the ferroelectric gate dielectric layer, and is configured to provide an on-state and an off-state for the ferroelectric field effect transistor through application of an on-voltage and an off-voltage, respectively, from a gate bias circuit. An energy level of the charge trapping band during the on-state is offset from an energy level of minority charge carriers of the semiconductor channel.

Abstract: A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.

Abstract: An improved dummy gate and a method of forming the same are disclosed. In an embodiment, the method includes depositing a first material in a trench, the trench being disposed between a first fin and a second fin; etching the first material to expose an upper portion of sidewalls of the trench; and depositing a second material on the first material without the second material being deposited on the exposed upper portion of the sidewalls of the trench.

Abstract: According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

Abstract: In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.

Abstract: A variable reluctance motor load mapping apparatus includes a frame, an interface disposed on the frame configured for mounting a variable reluctance motor, a static load cell mounted to the frame and coupled to the variable reluctance motor, and a controller communicably coupled to the static load cell and the variable reluctance motor, the controller being configured to select at least one motor phase of the variable reluctance motor, energize the at least one motor phase, and receive motor operational data from at least the static load cell for mapping and generating an array of motor operational data look up tables.

Abstract: A method of filling a recess according to one embodiment of the present disclosure comprises heating an amorphous semiconductor film without crystallizing the amorphous semiconductor film by radiating laser light to the amorphous semiconductor film embedded in the recess.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

Abstract: A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis.

Abstract: A device includes a plurality of bottom electrode features, a plurality of Magnetic Tunnel Junction (MTJ) stacks formed on top surfaces of the bottom electrode features, top electrode features formed on top of the MTJ stacks, and an etch stop layer extending along side surfaces of the bottom electrode feature and partially along side surfaces of the MTJ stacks.

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

Abstract: A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N?3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.