Abstract: Systems and methods for providing accelerated loading of operating system and application programs upon system boot or application launch are disclosed. In one aspect, a method for providing accelerated loading of an operating system comprises the steps of: maintaining a list of boot data used for booting a computer system; preloading the boot data upon initialization of the computer system; and servicing requests for boot data from the computer system using the preloaded boot data. In another aspect, a method for providing accelerated launching of an application program comprises the steps of: maintaining a list of application data associated with an application program; preloading the application data upon launching the application program; and servicing requests for application data from a computer system using the preloaded application data.

Abstract: Systems and methods are disclosed for providing accelerated loading of operating system and application programs. In one aspect, a method for providing accelerated loading of an operating system comprises the steps of: maintaining a list of boot data; preloading the boot data upon initialization of the computer system; and servicing requests for boot data from the computer system using the preloaded boot data. In a preferred embodiment, the boot data is retrieved from a boot device and stored in a cache memory device. In another aspect, a method for accelerated loading of an operating system comprises updating the list of boot data during the boot process, wherein updating comprises adding to the list any boot data requested by the computer system not previously stored in the list and/or removing from the list any boot data previously stored in the list and not requested by the computer system.

Abstract: A method, system and computer program product for reducing the collective power consumption of a plurality of storage devices including a plurality of associated storage volumes is provided. The storage volumes are grouped by a last access time according to a plurality of ranks. The plurality of ranks corresponds to a level of power consumption based on device activity. A volume of the plurality of storage volumes is moved between the plurality of ranks according to an access pattern of the volume.

Abstract: Backup applications that use externally connected hard disk drives for storing full image backups of a windows system disk or compressed image or file by file backups of a windows system disk. A system incrementally updates the images, including the system registry, and puts information on the external drive that makes it bootable.

Abstract: A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.

Abstract: A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti?1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

Abstract: Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.

Abstract: Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A method for implementing a remote basic input/output system (BIOS) on a multi-blade server is provided. A remote BIOS partition is created on a management module of the multi-blade server for each blade of the multi-blade server residing on the management module. BIOS settings for operation on a first blade of the multi-blade server are defined.

Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.

Abstract: An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

Abstract: A control apparatus controls a supply of power to a second apparatus that operates independently of a first apparatus, and includes a notifying part to make a notification that notifies a need to control the power supplied to the second apparatus if needed, based on a preset timer time and a present time acquired from a Real Time Clock (RTC) within the first apparatus, and a supplying part to supply information related to a time for controlling the power supplied to the second apparatus, based on the notification from the notifying part, wherein the notifying part and the supplying part are operable with a power that makes only limited functions within the first apparatus operable.

Abstract: An example embodiment is illustrated to reduce power consumed by inactive connections. This embodiment may include detecting a connection condition signifying a requirement for an active connection between one network device and another network device. Thereafter, an enable instruction may be retrieved based upon the detecting of the connection condition, and a port may be enabled based upon the retrieved enable instruction resulting in increased electrical power consumption by a port component. The electrical power consumption may be increased relative to a prior level of electrical power consumption in which the port is disabled.

Abstract: A computer system including a central processing unit (CPU), a chipset, a first bus, a second bus, a first memory, a second memory, and a logic control circuit is disclosed. The chipset is coupled to the CPU. The first bus and the second bus are respectively coupled to the chipset. The first memory is coupled to the chipset through the first bus for storing a first basic input output system (BIOS). The second memory is coupled to the chipset through the second bus for storing a second basic input output system (BIOS). The logic control circuit detects a state of the first bus and controls the chipset to select to access the first memory through the first bus or select to access the second memory through the second bus according to the state of the first bus.

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, comprising: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals, the plurality of frequency signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator, and transmitting selected frequency signals; and a plurality of differential units, each for receiving the selected frequency signals, applying a differential signal to the selected frequency signals, adding time stamps to the selected frequency signals, and outputting respective time stamped differential selected frequency signals.

Abstract: A method for adjusting setup default value of a basic input output system (BIOS) and a main board are provided. The main board offers a BIOS memory which includes a boot block and a main block. The boot block includes an adjusting table, and the main block includes an original setup default value and a dynamic table. The adjusting table is used to read the dynamic table, and the original setup default value is adjusted to be a customized setup default value according to the adjusting table and the dynamic table. Afterwards, the customized setup default value is stored in a setup value memory.

Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.

Abstract: A timer circuit for a mobile communication terminal includes a counter operating under a reference clock, a storage unit that stores a timer timeout time corresponding to a time measurement request when receiving the time measurement request from a CPU, and a comparator 104 that generates an interruption signal to the CPU 120 when the time corresponding to the output value of the counter is coincident with the timer timeout time stored in the storage unit. The storage unit stores a plurality of sets of timer timeout time corresponding to a plurality of time measurement requests, and a stored timer timeout time which is closest to the time corresponding to the output value of the counter is set to the timer timeout time to be compared by the comparator.

Abstract: A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Abstract: A USB connector cable includes a main cable having four separately formed wires, namely, a voltage wire, a first data transmission wire, a second data transmission wire and a ground wire, and a power cable having a voltage wire and a ground wire which are integrally and respectively formed with the voltage wire and the ground wire of the main cable. An electronic device is suitable to connect with a peripheral device and includes a circuit board, an interface and a load switch. The interface outputs a first current and at least one data signal to the peripheral device and the interface complying with a computer related standard defining a first current threshold. The interface located on said circuit board. The load switch connects to the interface and runs a second current to said interface. The load switch converts into a disconnected state while a value of the second current is excess than a second current threshold.