Abstract: The present invention relates to an information processing apparatus capable of executing plug and play processing for starting up one installation processing operation upon acquiring one device identification information item. The information processing apparatus includes an acquisition unit for acquiring at least one device identification information item including a plurality of configuration information items corresponding to each of a plurality of logical interfaces in response to connection of a peripheral device. The information processing apparatus further includes an installation control unit for controlling execution of installation of a plurality of device drivers corresponding to the plurality of logical interfaces, respectively, by the use of the plurality of configuration information items included in the at least one device identification information item when the acquisition unit acquires the at least one device identification information item from the peripheral device.

Abstract: A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associated transfer control information. Timing of receipt of the payload data by the recipient circuitry is controlled by the transfer control information. Timing easing circuitry located within the communication channel temporarily buffers the transfer control information before outputting it to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered. The number of clock cycles that elapses between the first clock cycle and the later clock cycle depends on the specified timing easing value. This enables a multi-cycle path to be provided to transfer the payload data.

Abstract: Software program or application can determine if the storage device it was launched from is connected to the host computer system on an internal bus or an external bus. The ability of a software application to determine from where it and the operating system was launched allows it to perform a plurality of actions based on the launch location such as limiting the functionality of an application depending on its launch location. If a software company does not want its software to be installed or executed from an external drive or executed on multiple computers then it can limit the users ability to moved the software from one computer to another on a portable drive connected through a USB or IEEE-1394 port.

Abstract: A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

Abstract: An application program is provided to work with two operating systems of a computer. A first mode of the application program is configured to work with the computer before the primary operating system is booted. The second mode of the application program is provided to work under the environment provide by the primary operation system.

Abstract: Disclosed is an application program which can directly access a transmit buffer of a serial port. Data written into the transmit buffer by the application program is transferred into a receive buffer of the serial port via a switching element. The computer BIOS is enabled to directly access the receive buffer and therefore read the data written by the application program. The state of the switching element may be controlled by the application program to selectively allow data transfer from the transmit buffer to the receive buffer. A jumper plug may be used to create a short circuit between the transmit buffer and the receive buffer instead of closing the switching element.

Abstract: A motherboard comprises a first unit which includes most components that are common in a group of motherboards which have a same chip set, a second unit which includes components that are different in the group of motherboards, and a BIOS Bin file which is loaded in the first unit. The BIOS Bin file comprises a share module, a loading module unit which includes a plurality of loading modules each corresponding to one type of motherboard, and a startup module which identifies the type of the motherboard according to a voltage of pre-selected GPIO Pins, and reads one of the loading modules corresponding to that type of motherboard to identify and initiate the second unit, and reads the share module to identify and initiate the first unit.

Abstract: One embodiment of the present invention provides a system that uses a directory service to facilitate centralized device naming. The system operates by receiving a registration of a device at a computer system. Next, the system determines if the device has been registered with the directory service. If so, the system retrieves a name of the device from the directory service. If not, the system generates a device name for the device, and registers the device name with the directory service.

Abstract: A system that controls one or more operating parameters in a computer system is presented. Until specified values for one or more operating parameters are achieved, the system performs the following operations. The system operates the computer system using a specified load profile. The system then determines whether the specified load profile produces the specified values for the one or more operating parameters. If the specified load profile does not produce the specified values for the one or more operating parameters, the system adjusts the specified load profile, which involves using a pulse-width modulation technique to adjust a duty cycle between a first workload and a second workload.

Abstract: In an information handling system (IHS), providing an IHS boot includes forcing the IHS to power on or reboot, retrieving a virtual serial peripheral interface (SPI) boot image using a virtual SPI bus, booting the IHS to the virtual SPI boot image, turning off the virtual SPI boot image, and updating a real SPI boot image.

Abstract: The present visibility-aware service reduces power-intensive activities when a window associated with the visibility-aware service is not visible. The window is not visible when the window is minimized or when the window is switched from a foreground position to a background position on a display.

Abstract: Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

Abstract: A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.

Abstract: A method for executing the power on self test (POST) on the computer system and a method for updating the SMBIOS information partially are provided for a computer system with a first memory and a second memory, wherein the first memory comprises a first storage block and a second storage block. A user can previously set the specific SMBIOS information in the second storage block. And during the POST stage, the default SMBIOS information in the BIOS code loaded from the first storage block to the second memory will be partially updated according to the specific SMBIOS information set by the user. As a result, the purpose of using the appropriated SMBIOS information to initiate the computer system can be achieved.

Abstract: The invention discloses a memory card control chip. The memory card control chip comprises a clock generator, a first memory card interface, and a control circuit. The clock generator generates a first clock signal and a second clock signal. The second clock signal is a spread spectrum clock signal. The first memory card interface is coupled to the clock generator and comprises a first clock signal pin and a plurality of first data signal pins. The first memory card interface is connected to a first memory card to be a data transmission interface of the first memory card. The first clock signal pin transmits the second clock signal. The control circuit is coupled to the first memory card interface and receives the first clock signal for performing the data accessing of the first memory card.

Abstract: A redundant power supply may obtain a rule for increasing mean time between failures (MTBF) for a first internal power supply and a second internal power supply connected to an electronic device, apply the rule to the first and second power supplies, activate the second internal power supply based on the rule to permit the second internal power supply to provide power to the electronic device, and deactivate the first internal power supply based on the rule.

Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A power saving method of a bi-directional communication wireless peripheral device includes providing a wireless communication protocol between a host and the bi-directional communication wireless peripheral device; establishing a bi-directional communication wireless link between the host and the bi-directional communication wireless peripheral device through the wireless communication protocol; and enter a power off mode when the bi-directional communication wireless link does not exist.

Abstract: A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

Abstract: A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device.