Abstract: A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management system in the receiving device then uses this information to adjust event information once the event is received.

Abstract: A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.

Abstract: A method and an apparatus to detect over clocking of a processor are illustrated. The over clocking detector may detect as to whether the system clock of a microprocessor is over clocked and then generate an over clocking indicator. The over clocking indicator may be stored and accessed at a later time. The over clocking indicator may be retrieved through a test access port.

Abstract: Shown is a method and system for provisioning a target computer with an operating system, which calls for booting the target computer in a pre-operating system environment, collecting configuration information for the target computer, and transmitting the configuration information to a predetermined server. The approach shown also provides for searching a database in the server for a pre-existing operating system image corresponding to the configuration information from the target computer. If a corresponding operating system image is found, then the present approach involves transferring the pre-existing operating system image to the target computer and installing the pre-existing operating system image on the target computer.

Abstract: A method for recovering a content of a basic input output system (BIOS) of a computing system, includes the steps of: providing an externally electrical connection to said BIOS and said computing system; providing an operable recovery source for said BIOS and connectable with said computing system via said externally electrical connection; recording recovery information from said recovery source via said externally electrical connection; and switching said externally electrical connection of said recovery source to another electrical connection between said BIOS and said computing system so as to replace said content of said BIOS by said recovery information.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: An exemplary computer-automated method is disclosed. The computer-automated method may include determining a plurality of commands. The plurality of commands may include first and second commands. The computer-automated method may also include performing an iterative execution process. The iterative execution process may include executing the first command on a computer and determining whether the computer performed a power management operation in response to the first command. The iterative execution process may end when the computer performs the power management operation in response to the first command. The iterative execution process may execute the second command when the computer fails to perform the power management operation in response to the first command.

Abstract: The power consumed by a memory is reduced without affecting the performance whereby a processor accesses the memory. A state of a power supplied to the memory is controlled to one of an active state wherein a storage area included in the memory rank can be accessed from the processor, and an inactive state wherein access cannot be performed without a delay for each memory rank, the basic system software prevents fragmentation in which the allocated storage area spans a plurality of memory ranks, puts the power state of a memory rank which does not include an allocated storage area into the inactive state, and puts the power state of a memory rank which includes a storage area required for allocation first into the active state.

Abstract: One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.

Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU, wherein the VID signal line set includes a least significant bit (LSB) signal line set and a most significant bit (MSB) signal line set. The core voltage controller conforms to a second standard and is coupled to the MSB signal line set to determine the core voltage to be output to the CPU according to the bit state of each MSB signal line in the MSB signal line set, so that the power supply system can conform to the first standard.

Abstract: Adaptive voltage control. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor. An efficient voltage for operating the microprocessor at said desirable operating frequency is computed. The microprocessor is operated at the efficient voltage.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: An indication that a power supply is ramped up to a threshold level is received. A circuit is woken up in response to receiving the indication if a control field of configuration information is in a first state, and the circuit is not woken up in response to receiving the indication if the control field of configuration information is in a second state.

Abstract: A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.

Abstract: An apparatus including an electrical energy storage device arranged to provide an output voltage that decreases with time; a reference clock; and a multi-mode controller having a first mode in which the reference clock is disabled and a second mode in which the reference clock is enabled, the multi-mode controller being operable, when in the first mode, to monitor a voltage provided by the electrical energy storage device and to change the mode of the controller from the first mode to the second mode when the monitored voltage falls beneath a threshold value and being operable, when in the second mode, to enable storage of electrical energy in the electrical energy storage device.

Abstract: A micro-controller includes a USB control unit, an MC unit having an operation mode and a stop mode and an oscillating circuit, which is commonly used by the USB control unit and the MC unit. The USB control unit includes a watching circuit for watching a condition of a first data and a second data, which is complement data of the first data. The operation of the oscillating circuit is controlled in response to an operation control signal, which is generated by a watching result, and an oscillation control signal whose voltage level is changed in response to the mode of the MC unit.

Abstract: Briefly, a processor and a method of estimating an active energy consumption of two or more cores of a processor based on dispatching micro operations to one or more execution units of the processor.