Abstract: A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate.

Abstract: A power supplying mode switching controller is disclosed. The power supplying mode switching controller includes a main controller which controls an image forming apparatus, a power supply circuit which has a normal mode and a power saving mode, an I/O controller which switches the power supply circuit to the normal mode when a factor returning to the normal mode is generated in the power saving mode, and an SD interface to which an SD card is attached. The I/O controller includes a first attaching change detecting circuit which detects an attaching change of the SD card to the SD interface, and when the first attaching change detecting circuit detects the attaching change of the SD card to the SD interface in the power saving mode, the I/O controller switches the power supply circuit to the normal mode and informs the main controller of the attaching change of the SD card.

Abstract: Memory storage apparatus include a non-volatile memory for storing data and a power management unit configured to sense a level of an external power supply and to predict a loss of the external power supply. A power-polling time control circuit is configured to control a time when a voltage level sourced from the external power supply is reduced below a predetermined level after loss of the external power supply. A control logic controls read and/or write operations of the non-volatile memory responsive to a prediction of loss of the external power supply from the power management unit.

Abstract: A method of powering up a portable terminal, which automatically executes a software program when powered on, the terminal having a manually operated power-up key, wherein the method comprises the step of: a) at the beginning, moving (in 32) the key from an idle position in which the terminal is powered off to an active position in which the terminal is powered up, then b) before a first predetermined time interval (?1) has elapsed since the beginning of step a), starting (in 36) to run the software program on the terminal, the first time interval being long enough to check that the key has not been inadvertently moved, then c) when the first time interval elapsed, if the key is still in the active position, continuing (in 42) to run the software program, else powering down the terminal (in 40).

Abstract: A fingerprint reader resetting method comprising enabling an electronic device to accept a reset command for a fingerprint reader in response to a physical presence state being set to unlocked during initialization of an electronic device to reset a state of the fingerprint reader.

Abstract: An electronic device comprising a host module and a wireless module each comprising a processing unit, wherein the electronic device is configurable to be operated in a low processing mode by performing processing functions for the electronic device using the processing unit of the wireless module.

Abstract: In one embodiment, the present invention includes a method for receiving a request for power-up of a first blade of a chassis, enabling the first blade to power-up in a reduced boot mode and receiving a communication including characteristic information and policy information associated with the first blade, and analyzing the characteristic information and the policy information to determine a policy and a boot configuration for the first blade. Other embodiments are described and claimed.

Abstract: An operating system in a virtual environment can obtain the current time of the processor that the OS is utilizing through a method for synchronizing timers on multiple processors with a standard reference time, such as the Coordinated Universal Time (UTC). A hypervisor controlling the processors obtains a number of synchronization values that, together with a local timer counter value, are utilized by the guest operating system to determine the physical processor time.

Abstract: A system and method for power over Ethernet (PoE) provisioning for a computing device using a network profile. Various types of power management information can be used in a process for determining a power request/priority. Power management information such as user information or device information can be stored in a profile in a network database. This network database can be accessed by a switch in determining a power request/priority for a computing device.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.

Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.

Abstract: The present invention is to provide a network system for transmitting various signals and power, which comprises at least a power sourcing equipment and at least a powered device over a network. Each of the power sourcing equipment and the powered device has at least a port, wherein a first isolated conductor is disposed at one side of the port while a second isolated conductor is disposed at the other side of the port and creates a power circuit for transmitting power in combination with the first isolated conductor. Four differential signal pairs of the port, each with two conductors, are disposed between the first isolated conductor and the second isolated conductor, wherein each of the power sourcing equipment and the powered device transmits Ethernet signals through two of the differential signal pairs of its port and transmits other network signals through the other two differential signal pairs.

Abstract: A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.

Abstract: Requests to an operational module are received at a monitoring device, where an estimated amount of energy expected to be consumed by the operational module while executing operations related to requests is accumulated for a sliding time window. A throttle signal is generated to limit the amount of energy consumed by the operation module is generated when the accumulated amount exceeds a maximum amount.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: An accelerated boot process for a multiprocessor system and system components for use with the process are disclosed. Each processor caches at least one compressed system image in local nonvolatile memory. The processors boot concurrently, each using a local image. After a master processor is booted, the other processors verify with the master that each has booted a correct image version. Various redundancy and fallback features are described, which guarantee that all cards can boot and operate even if the preferred local system image contains a defect.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A power management system for use in a laptop computer and its power management method include an external power apparatus and a control unit and a switch disposed in the laptop computer. The external power apparatus is pluggable and supplies direct current (DC) between 5 and 1.8 DC voltages to the laptop computer. The switch can turn on/off the direct current to at least one DC voltage point within the laptop computer based on a control signal sent from the control unit.

Abstract: In some embodiments, the invention involves system and method for resuming from sleep mode using protected storage accessible to an embedded controller. The boot script information is stored in memory that is available only to the embedded controller. Neither the firmware nor OS have access to the boot script. Upon a wake event, the embedded controller either plays the boot script itself, or sends the information to firmware for processing. Other embodiments are described and claimed.

Abstract: Firmware FW1 and FW2 is separately stored in a non-volatile memory, in which a boot code for start-up and a restoration code are stored, and a first magnetic disk. A copy of the firmware FW1 stored in the non-volatile memory is stored in the first magnetic disk, and a copy of the entire firmware FW1 and FW2 stored in the first disk medium is stored in the second magnetic disk. When an error occurs during firmware update, upon next power-on, whether the volatile memory, the first magnetic disk, and the second magnetic disk are normal or abnormal is determined, and valid firmware is read and allocated to the volatile memory so as to perform start-up by a start-up mode corresponding to the determination contents.