Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.

Abstract: A method and apparatus for communicating with a device is provided. A user views a graphical user interface displayed on a client. For example, the graphical user interface may correspond to a web page or a graphical user interface of an operating system. The graphical user interface may display an icon. The display of the icon may indicate, to the user, whether a device, associated with the icon, is in an energy-saving mode. The user may configure the icon to cause the client to issue requests to the device. A request, sent from the client to the device, may instruct the device to exit the energy-saving mode. In this way, the user may instruct a device to exit the energy-saving mode (i.e., to “wake-up”) prior to issuing a request for the performance of a service (such as a request to print an electronic document) to the device.

Abstract: A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.

Abstract: Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

Abstract: A method of transitioning between an active mode and a power-down mode in a processor-based system includes saving a state of the active mode, detecting the occurrence of one or more interrupt events during a transition between the active mode and the power-down mode, and responding to the detected interrupt events.

Abstract: A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.

Abstract: Provided are a method, system, and article of manufacture, wherein instructions stored in an option ROM are copied to the system memory of a computer, wherein the option ROM corresponds to a device that is coupled to the computer. A virtual machine is generated, wherein the virtual machine executes the instructions copied to the system memory to boot the device before any operating system is loaded.

Abstract: An electronic apparatus, capable of efficiently supplying power in accordance with execution process analysis of the electronic apparatus and classification of externally connected external equipment, includes an equipment connection section for connecting with multiple external equipments, a process judgment section for making a judgment as to a process to be performed by the electronic apparatus, an equipment selection section for selecting external equipment based on the judgment result of the process judgment section, and a power supply section for supplying power to the external equipment selected by the equipment selection section.

Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A scaling factor used in time interpolation calculations is tuned so as to compensate for clock sources that generate timer interrupts both slower and faster than expected. The scaling factor is decreased when the timer interrupts are late and the scaling factor is increased when the timer interrupts are early. By being able to account for timer interrupts that are generated too early, time skips are minimized. The adjusted scaling factor is used in calculating system time and interpolation offset values.

Abstract: The present invention discloses a method for updating the timing of a baseboard management controller (BMC) applied in a computer system. When a basic input output system (BIOS) installed on a motherboard of the computer system is initialized, the current time for the BMC to receive the BIOS is used for the timing of the BMC, and the BMC will send regular synchronous signals to the motherboard at a predetermined interval thereafter. After the motherboard has received the synchronous signal, the current time of the BIOS is sent to the BMC, and the BMC updates the timing of the BMC by the current time of the BIOS, so that the timing of the BMC will be consistent with the current time of the BIOS, and system administrators no longer need to update the time manually.

Abstract: A method and apparatus for compensating for a delay in the propagation of a plurality of signals via different signal paths, i.e., a skew compensation method, are provided. The apparatus includes a processing circuit which performs a data processing operation on input data, and a reset adjustment circuit which maintains a reset state of the processing circuit for a time period when a reset signal that initializes the processing circuit is received.

Abstract: An apparatus for controlling an active cycle of semiconductor memory that supports a synchronous mode and an asynchronous mode is provided. The apparatus includes an operational mode control unit that determines the operational mode of the semiconductor memory on the basis of a clock signal for a predetermined time and outputs an operational mode determination signal, and an active control unit that controls the output of an active signal for executing an active cycle of the corresponding operational mode on the basis of the operational mode determination signal.

Abstract: A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract: A method of adjusting power budgets of multiple servers within a data center comprises various actions. Such actions include, for example, organizing the multiple servers into hierarchical groups, dividing a total power budget among the hierarchical groups, and assigning power consumption levels to individual members of a particular hierarchical group such that the sum total of the assigned power consumption levels does not exceed the total power budget for the particular hierarchical group. The act of dividing is dynamic with respect to time.

Abstract: A power management technique for a network including a plurality of computing devices. The power management technique includes identifying an order in which one or more devices of the plurality of computing devices can transmit data within the prescribed time period. In one aspect, the number of wakeups are reduced for the computing devices within the network by increasing a number of adjacent channel time allocation periods within a prescribed time period that share a common computing device. In one aspect, the network can be based on Time Division Multiple Access (TDMA).

Abstract: A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronize the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronization signals generated by the control processor (16), thereby minimizing the power consumption of the SIMD processor architecture (2).

Abstract: A data processing system supports a virtualization enabled (VE) operating mode. An operating system (OS) is launched during a boot process. However, a trap agent is launched before the OS is launched. The trap agent may intercept an attempt to transition the data processing system to virtual machine (VM) operating mode. In response to intercepting the attempt to transition the data processing system to VM operating mode, the trap agent may automatically determine whether the program that requested the transition is an authorized program. If the program is not authorized, the trap agent may prevent the program from transitioning the data processing system to VM operating mode. In one embodiment, the trap agent is launched before the data processing system selects a boot device. In another embodiment, the trap agent is launched before executing any code from any third-party option ROMs. Other embodiments are described and claimed.