Abstract: The invention relates to a non-transitory computer program product, a method and an apparatus for managing garbage collection process. The non-transitory computer program product includes program code to: determine source blocks to be processed, wherein each source block includes an invalid page; program user data of valid pages in the source blocks, whose quantity is less than a total number of pages in one first-type physical block, into empty pages in a second-type physical block, wherein the total number of pages in one first-type physical block is greater than a total number of pages in one second-type physical block; and fill remaining empty pages in the second-type physical block with dummy values.

Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.

Abstract: A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.

Abstract: A memory system, a memory controller, and an operating method therefor. The memory system includes a first processor configured to determine a processor, among multiple processor including the first processor, to process read operations on logical addresses indicated by read commands, and process a write operation on a logical address indicated by a write command; and a second processor, among the multiple processors, configured to process a read operation on a target logical address selected by the first processor among the logical addresses. The first processor searches for mapping information on a logical address corresponding to a read or write operation to be processed by the first processor, by using a first map search engine, and the second processor searches for mapping information on the target logical address by using a second map search engine. It is possible to improve the performance of searching for mapping information in a read operation.

Abstract: A system and method of managing storage on non-volatile memory (NVM) storage media, by at least one processor, may include receiving, from at least one client computing device, one or more data write requests, associated with application metadata, to store one or more respective data objects on the NVM storage media; performing a first classification of the one or more data objects, based on the application metadata, so as to associate each data object to a group of data objects; storing the data objects of each group in a dedicated storage set of a logical address space; and transmitting, or copying the data objects of each storage set to be stored in a respective, dedicated range of the NVM storage media.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.

Abstract: A method, system, and computer program product for encoded virtual block deferred reference counting comprising receiving an input/output (“IO”) request for data, the data associated with a virtual block, updating a reference count structure to reflect the IO request, and updating, out of line from the IO request, one or more reference counts associated with the virtual block to reflect the result of the IO request based on the updated reference count structure.

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device.

Abstract: A computational device receives a command to activate a time lock for a data set. In response to receiving the command to activate the time lock for the data set, a point in time copy of the data set is generated to allow write operations to be performed even if the time lock is activated.

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

Abstract: A computing device requests access to an application object from a remote storage system in order to locally execute application functionality without hosting application resources. An accessed object is associated with an intent in the storage system and locked. Locking an object in combination with an intent prevents computing devices that are not performing the intent from accessing the object. An intent defines one or more operations to be performed with the requested object, which are serialized as intent steps and stored in the storage system. Upon executing an intent step, the computing device stores a log entry at the storage system signifying the step's completion. A locked object remains locked until the log entries indicate every intent step as complete. Different computing devices can unlock a locked object by executing any incomplete steps of an intent associated with the locked object.

Abstract: A data management method, a memory storage device and a memory control circuit unit. The method includes: executing one or more read commands, and recording a physical unit having a first variation of a read count greater than a read disturb threshold as a risk physical unit; and when a data merging process is performed, dividing valid data stored in the risk physical unit into a plurality of copies and copying the copies into a plurality of recycling units.

Abstract: A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

Abstract: The present disclosure relates to an electronic device. A storage device having improved memory block use efficiency includes a plurality of memory blocks each including a plurality of pages storing data, an erase page storage configured to store erase page information about erase pages in a victim block among the plurality of memory blocks and a bad block controller configured to replace a fail page in which a program fail occurred with one of the erase pages, based on the erase page information, the fail page being one of the plurality of pages in one of the plurality of memory blocks other than the victim block.

Abstract: One example method includes discovering an application instance on a host, reporting the existence of the application instance, discovering application components of the application instance, and mapping the application components to information concerning an underlying filesystem and information concerning an underlying physical drive. The example method additionally includes freezing the application instance in response to a first instruction, and then thawing the application instance in response to a second instruction.

Abstract: A system comprising integrated circuit (IC) dice having memory cells and a processing device coupled to the IC dice. The processing device to perform operations including: intercepting an input/output (IO) write request directed at the IC dice; causing a device mapping logic to enter an initial state associated with a first group of memory cells of the IC dice; caching a write pointer that includes a location within the first group of memory cells; transitioning the device mapping logic from the initial state to a sequential IO state; and, in response to determining the IO write request is directed to the location of the write pointer, causing data associated with the IO write request to be sequentially written to IC dice starting at the location of the write pointer.

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.