Abstract: A data processing system comprises a host that includes a first memory; and a memory system that includes a controller having a second memory, and a memory device, wherein the controller: checks whether a first mapping table whose mapping information is changed exists or not in a first list, checks whether a memory block corresponding to a piece of map data included in the first mapping table exists or not in a second list, and decides that the first mapping table is to be shortly updated due to an internal operation and does not transfer the first mapping table to the host when the memory block corresponding to the map data included in the first mapping table exists in the second list.

Abstract: An apparatus, a computer program and a method for prefetching a predetermined number of data items to a cache. The method comprises obtaining a list of candidate data items and associated scores thereof, that comprises more candidate data items than the predetermined number of data items to be prefetched to the cache. The method comprises repeatedly selecting, based on scores of the candidate data items, a candidate data item from the list and determining whether to add the candidate data item to the cache. Determining whether to add the candidate data item to the cache comprises determining whether the candidate data item is retained by the cache; and in response to determining that the candidate data item is not retained by the cache, adding the candidate data item thereto. The repeatedly selecting and determining are performed until the predetermined number of data items is added to the cache.

Abstract: A method is applied to an electronic device, all storage space of the electronic device includes internal storage space and at least one external storage space, and the method includes: receiving a data write instruction, where the data write instruction carries target write data; selecting at least one of all the storage space as target storage space according to a preset rule, and performing a write operation in the target storage space; and after the write operation is completed, updating a virtual file that is obtained by summarizing and combining files of a same file type in all the storage space of the electronic device and that is stored in a virtual storage card, and updating a mapping relationship between a virtual storage path corresponding to the virtual storage card and a physical storage path corresponding to the target storage space.

Abstract: Examples disclosed herein relate to a storage appliance using an optimistic allocation of storage space. In an example system, a number of storage drives are coupled to a storage controller and a RNIC (remote direct memory access (RDMA) network interface card (NIC)) through a storage network. The RNIC includes a layout template selector and a plurality of templates. The layout template selector selects a layout template based, at least in part, on a logical block address (LBA) received from a host. The layout template identifies each of a number of storage drives associated with portions of data represented by the LBA. The controller includes a virtualization computation module to determine a new layout template for the data represented by the LBA and the new layout template.

Abstract: A selection device can be operatively coupled with non-volatile memory devices. Enable signals that are based on an architecture of non-volatile memory devices can be received. Data can be transmitted to the non-volatile memory devices based on the enable signals that are based on the architecture of the non-volatile memory devices.

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

Abstract: Disclosed herein is an apparatus and method for a distributed memory object system. In one embodiment, a method includes forming a system cluster comprising a plurality of nodes, wherein each node includes a memory, a processor and a network interface to send and receive messages and data; creating a plurality of sharable memory spaces having partitioned data, wherein each space is a distributed memory object having a compute node, wherein the sharable memory spaces are at least one of persistent memory or DRAM cache; at a client, establishing an inter process communication between the client and a distributed memory object service; receiving a meta chunk including attributes about a file and a chunk map from a distributed memory object service, wherein the meta chunk includes chunk information including identity and location of a data chunk; and the client mapping the data chunk into virtual memory address space and accessing it directly.

Abstract: The disclosure provides an approach for zeroing allocated storage blocks of a file. The blocks are zeroed in the background, during a normal operation of a storage system, thus lowering the chance that the latency of a storage operation would be increased by the zeroing process. The approach also precludes a delay in being able to use the file, the delay caused by pre-zeroing the storage blocks prior to use of the file.

Abstract: A metadata management method for a memory device includes generating a virtual address layer in a memory space of a non-volatile memory of the memory device; establishing a mapping table in the virtual address layer to store at least one metadata corresponding to at least one storing block, wherein the at least one storing block comprises at least one physical address and the at least one physical address is related to the memory space; when writing at least one datum to the memory device, writing the at least one datum to at least one memory block of the memory space according to the at least one physical address; and updating the at least one metadata of the at least one storing block when finishing writing the at least one datum.

Abstract: The embodiments of the present invention relate to a storage system comprising: a storage network; at least two storage nodes, connected to the storage network; and at least one storage device, connected to the storage network, each storage device comprising at least one storage medium; wherein, the storage network is configured to enable each of the at least two storage nodes to access any of the at least one storage medium without passing through another storage node of the at least two storage nodes. According to the embodiments of the present invention, a storage system in which there is no need to physically migrate data when rebalancing is required is provided.

Abstract: A memory sharing dual-mode network communication device includes a first memory, an OTT module and a PON module. The first memory is divided into an OTT region and a PON region, and the OTT module is used to obtain an OTT service, which includes an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit, and a memory slave controller. The PON module includes a PON processor and a second memory main controller. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request of the PON processor to access the OTT area or the PON area of the first memory through the first memory host controller, and the memory arbitration circuit further determines the priority order of the first access request and the second access request.

Abstract: An agent for managing virtual machines includes a persistent storage and a processor. The persistent storage stores backup/restoration policies. The processor identifies a virtual machine of the virtual machines that is likely to fail and, in response to identifying the virtual machine, identifies backup data associated with the identified virtual machine; instantiates a clone of the identified virtual machine using the identified backup; exposes the clone while the identified virtual machine is exposed; and hides the virtual machine after the clone is exposed.

Abstract: Techniques for management of IS memory in a non-volatile storage device, and methods for use therewith, are described herein. The non-volatile storage device can include non-volatile memory, wherein a portion of the non-volatile memory is designated as intermediate storage (IS) memory and another portion of the non-volatile memory is designated as main storage (MS) memory. The IS memory may have lower read and write latencies than the MS memory. A host device may provide priority addresses to a memory controller with an indication that host data having one of the priority addresses is to receive priority to remain in IS memory over other host data.

Abstract: An information processing apparatus that includes a memory that is configured to store written information and to store a writing program for writing information to the memory; and an electronic control unit that is configured to write information to the memory in accordance with the writing program stored in the memory, wherein: the memory stores a disabling program for disabling overwriting of the information stored in the memory, the electronic control unit disables overwriting of the information stored in the memory in accordance with the disabling program stored in the memory for disablement when writing of the information executed by the electronic control unit is finished, the memory stores reference information to be referred to when the electronic control unit executes writing of information, and the electronic control unit overwrites the reference information stored in the memory with information that is unrelated to the reference information.

Abstract: A memory access method for selectively creating a simplified mapping table includes the steps of: selecting one of a plurality of partitions of an original mapping table so as to use one physical page address in a selected partition as a start physical page address; scanning each entry of the selected partition so as to search a randomly mapped entry in the selected partition; determining whether a memory space required for creating the simplified mapping table is smaller than a memory space required for the selected partition; and selectively storing the start physical page address, the number of the randomly mapped entries, and a logical page address and a physical page address recorded on each randomly mapped entry according to the determination result of the determining step so as to create a simplified mapping table.

Abstract: A method for providing block access on top of a key-value store comprising a distributed data storage system is provided. The method can include receiving, at a block device, a first input/output operation requesting one or more data blocks. The first input/output operation can be translated into a second input/output operation requesting one or more key-value pairs. The second input/output operation can be performed by at least sending the second input/output operation to the key-value store. Related systems and articles of manufacture, including computer program products, are also provided.

Abstract: In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Abstract: A computing device requests access to an application object from a remote storage system in order to locally execute application functionality without hosting application resources. An accessed object is associated with an intent in the storage system and locked. Locking an object in combination with an intent prevents computing devices that are not performing the intent from accessing the object. An intent defines one or more operations to be performed with the requested object, which are serialized as intent steps and stored in the storage system. Upon executing an intent step, the computing device stores a log entry at the storage system signifying the step's completion. A locked object remains locked until the log entries indicate every intent step as complete. Different computing devices can unlock a locked object by executing any incomplete steps of an intent associated with the locked object.