Patents Examined by Tasnima Matin
  • Patent number: 11042452
    Abstract: A method for storage system reliability using data recovery as a service, the method including: receiving, for storage data on a storage system, a specification for a particular recovery time objective (“RTO”) and recovery point objective (“RPO”) setting among a plurality of options for RTO/RPO settings; generating, in accordance with the particular RTO/RPO setting, a change stream of data in response to receiving data to be stored on the storage system; and transmitting, from the storage system to a cloud data recovery as a service endpoint, the change stream of data from which data on the storage system may be recovered up to a point in time corresponding to the particular RPO setting and within a time period corresponding to the particular RTO setting.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 22, 2021
    Assignee: Pure Storage, Inc.
    Inventor: Gregory McNutt
  • Patent number: 11036642
    Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Dimitrios Ziakas, Mark A. Schmisseur, Kshitij A. Doshi, Kimberly A. Malone
  • Patent number: 11029875
    Abstract: A data storage system includes an accelerator pool and data silos. The accelerator pool obtains a data storage request for first data; stores a copy of the first data locally in a memory of the accelerator pool; in response to storing the copy of the first data: sends an acknowledgement to a requesting entity that generated the data storage request; and, after sending the acknowledgement, stores at least one second copy of the first data in the data silos. The acknowledgement indicates that the first data is redundantly stored in at least two different fault domains.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Dell Products L.P.
    Inventors: Dharmesh M Patel, Rizwan Ali, Ravikanth Chaganti
  • Patent number: 11023170
    Abstract: A writing method for a solid state drive is provided. Firstly, a buffer is divided into plural buffering regions corresponding to plural data streams. Then, the write command is received from a host, and a write data corresponding to the stream information of the write command is stored into the corresponding buffering region of the buffer. Then, the write data in each buffering region of the buffer is divided into plural groups according to a program data amount. Then, one program command is assigned to each group in each buffering region, the program command and each group are combined as a job, and the job is listed in a stream job link list. Afterwards, the jobs corresponding to each data stream are transmitted to a non-volatile memory according to a content of the stream job link list.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Hu
  • Patent number: 11023370
    Abstract: A memory system includes a non-volatile memory having a plurality of memory chips, a plurality of switches provided for each of the memory chips for switching on and off supply of power to the corresponding memory chip, and a memory controller configured to control the switches and data access to the non-volatile memory. The memory controller is further configured to determine whether there is a first memory chip among the plurality of memory chips that has no data item stored therein with an elapsed time from a most recent access thereof that is less than a threshold value, and if so, turn off the supply of power to the first memory chip while maintaining the supply of power to the plurality of memory chips other than the first memory chip.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Ryo Takeuchi
  • Patent number: 11010103
    Abstract: The described methods, systems, and other aspects can advantageously provide balanced multi-stage processing of non-uniform object data. An example method may receive a list of buckets. Each of the buckets in the list of buckets can store one or more restorable objects. The method further comprises distributing the list of buckets to the two or more second nodes; determining a number of the one or more restorable objects in each bucket; determining a size of the one or more restorable objects in each bucket; generating batches of to-be-restored data objects based on the determined number of the one or more restorable objects in each bucket and the determined size of the one or more restorable objects in each bucket; and distributing the batches among the two or more second nodes for storage-related task processing.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ameet Pyati, Souvik Roy, Tomy Ammuthan Cheru, Muhammad Tanweer Alam
  • Patent number: 11003364
    Abstract: Methods and systems for improving the performance of a write-once read-many (WORM) compliant data storage cluster in which a set of data (e.g., one or more electronic files) stored within the data storage cluster may be made immutable for a data retention time period are described. The data storage cluster may determine whether to lock the set of data to satisfy WORM compliance using a combination of software-based and hardware-based techniques depending on the required data retention time, the size of the set of data to be locked, the cost to move the set of data to WORM compliant hardware storage, and the amount of available disk space corresponding with WORM compliant hardware storage located within data storage nodes of the data storage cluster. Over time, the data storage cluster may repurpose data storage resources within the data storage cluster in order to satisfy WORM compliance.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: RUBRIK, INC.
    Inventor: Sahil Chauhan
  • Patent number: 11003369
    Abstract: Performing a tune-up procedure on a storage device including determining, during a boot process, that a first storage device is available for a tune-up procedure, wherein the tune-up procedure prepares the first storage device for use after being offline; reserving the first storage device to perform the tune-up procedure, wherein reserving the first storage device prevents another system from performing the tune-up procedure on the first storage device; and executing the tune-up procedure on the first storage device.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, Wei Tang
  • Patent number: 11003381
    Abstract: Provided is a storage device including a first non-volatile storage media having first performance capabilities; a second non-volatile storage media having second performance capabilities different from the first performance capabilities; and a device controller configured to report to a host software the first performance capabilities, the second performance capabilities, changes to the first performance capabilities, and changes to the second performance capabilities.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gunneswara R. Marripudi, Vishwanath Maram
  • Patent number: 10997085
    Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eri Ogawa, Takanori Ueda
  • Patent number: 10977172
    Abstract: Techniques are disclosed relating to virtual memory page reclamation policies. In some embodiments, an operating system of a computing device implements, during a first operating mode, a first page reclamation policy for pages corresponding to user processes and non-user processes. The computing device may then enter a second operating mode upon detecting some indication of user inactivity. The operating system may then implement, during the second operating mode, a second page reclamation policy for pages corresponding to user processes and non-user processes, where the second page reclamation policy prioritizes, relative to the first page reclamation policy, eviction of pages corresponding to non-user processes.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventors: Lionel D. Desai, Benjamin C. Trumbull
  • Patent number: 10970205
    Abstract: An example apparatus comprises a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device The first L2P data structure and the second L2P data structure may have a same size associated therewith.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Paolo Amato
  • Patent number: 10942820
    Abstract: Embodiments are described for performing an uninterrupted restore in a storage system in view of one or more abort events. A restore agent receives writes one or more data blocks to a conditional construction container. A parent interrupt service routine (ISR) polls for abort events. In response to an abort event, an intermediate interrupt is generated that spawns a child processes for each process of the restore. The intermediate ISR logs each child ISR, the process it is responsible for, and the intermediate interrupt, for later restoration of the restore state. After a recovery of the above event, then each child ISR can be called to restore its state. After restoring the state, the restore agent resumes the restore from where the abort event was detected. The child ISRs are re-entrant. If another abort event is detected, the restore state can again be saved and later resumed from that state.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 9, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mahesh Reddy A V, Battal Chetan, Mahantesh Ambaljeri, Swaroop Shankar D H
  • Patent number: 10942852
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for data processing and storage. One of the method includes: maintaining a plurality of tiers of storage devices and one or more tiers of caches by a storage system for storing blockchain data, the plurality of tiers of storage devices including at least a higher-tier storage device and a lower-tier storage device; determining that a blockchain data object in a data log file stored in a lower-tier storage device is an active data object, wherein the blockchain data object is block data, transaction data, or state data; and writing the blockchain data object into a cache of the one or more tiers of caches.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 9, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Shikun Tian
  • Patent number: 10936240
    Abstract: A computer-implemented method, according to one embodiment, includes: selecting two previously captured snapshots and calculating a checksum for each file in each of the two snapshots. The checksums are used to determine whether the two snapshots are sufficiently similar to each other. In response to determining that the two snapshots are sufficiently similar to each other, important ones of the files in each of the two snapshots are identified. The identified important files which are located in a lower performance tier of a multi-tier data storage system are transitioned to a higher performance tier of the multi-tier data storage system. Moreover, a merged snapshot is created by merging the two snapshots, and the merged snapshot is provided for additional operations. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Abhishek S. Dave, Shailesh S. Jeurkar, Sandeep R. Patil, Sasikanth Eda
  • Patent number: 10936218
    Abstract: Facilitating transmission of multi-segment data portions for storage devices is provided herein. A system can comprise a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can comprise sending a read request for object data associated with an object, wherein the object data comprises multiple segments distributed across nodes of a storage cluster. The operations also can comprise receiving an out of order transmission that comprises the multiple segments. Further, the operations can comprise ordering segments of the multiple segments based on respective packet sequence numbers associated with the segments, resulting in a properly ordered object data. According to some implementations, the respective packet sequence numbers can be respective precalculated ranges of packet sequence numbers associated with the segments of the multiple segments.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aleksandr Rakulenko, Mikhail Danilov
  • Patent number: 10915254
    Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
  • Patent number: 10915456
    Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
  • Patent number: 10908823
    Abstract: Methods, systems, and devices for data transfer for wear-leveling are described. Data may be stored in pages of banks and the banks may be grouped into bank clusters. A host device may address one bank of a bank cluster at a time. Data may be transferred from a bank to a buffer or a different bank cluster for wear-leveling purposes and this data transfer may take place opportunistically while a second bank, which may be in the same bank cluster, is being accessed based on an access command.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 10895983
    Abstract: A memory profiling system can generate profiles for target memory units of a memory component during runtime of the memory component. The memory profiling system can identify target memory units based on trigger conditions such as memory units crossing a specified depth in error recovery, receipt of a vendor specific (VS) command, memory unit retirement, or excessive background scan rates. In some cases, the memory profiling system can identify additional target memory units that are related to identified target memory units. The characterization processes can include computing voltage threshold (vt) distributions, Auto Read Calibration (ARC) analysis, Continuous Read Level Calibration (cRLC) analysis, DiffEC metrics, or gathering memory component metrics. The memory profiling system can store the generated profiles and can utilize the generated profiles to adjust operating parameters of one or more memory elements of the memory device, in real time.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Francis Chew, Bruce A. Liikanen