Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

Abstract: A data storage apparatus includes a cache memory module and a NAND flash memory module including a cache memory mirror and a user data storage zone. The cache memory module is connected to the cache memory mirror via a path and electrically connected to the user data storage zone via another path. The cache memory module receives a write command that includes user data from a host, writes a copy of the user data into the user data storage zone in a write-back mode, and writes another copy of the user data cache memory mirror in a write-through mode. If some of the user data are lost from the cache memory module before they are written into the user data storage zone, the user data written in the cache memory mirror are copied and written into the cache memory module when the data storage apparatus is initiated again.

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

Abstract: An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.

Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.

Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.

Abstract: Techniques are disclosed for dynamic memory allocation in a machine learning anomaly detection system. According to one embodiment of the disclosure, one or more variable-sized chunks of memory is allocated from a device memory for a memory pool. An application allocates at least one of the chunks of memory from the memory pool for processing a plurality of input data streams in real-time. A request to allocate memory from the memory pool for input data is received. Upon determining that one of the chunks is available in the memory pool to store the input data, the chunk is allocated from the memory pool in response to the request.

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

Abstract: An apparatus may include a virtual flash device configured to emulate a flash memory device. The virtual flash device may include a flash interface configured to communicate with a flash controller, an address translation module configured to translate memory addresses from a flash based memory space to another memory space of another memory, a metadata and control module configured to manage metadata from the emulation of the flash memory device, and a non-flash memory controller configured to communicate with the other memory.

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. Circuitry is configured to relocate the data of the first portion that is associated with one of the first number of logical block addresses to one of the two physical blocks of cells that don't have data stored therein, and relocate the data of the second portion that is associated with one of the second number of logical block addresses to the other one of the two physical blocks of cells that don't have data stored therein.

Abstract: One example method includes discovering an application instance on a host, reporting the existence of the application instance, discovering application components of the application instance, and mapping the application components to information concerning an underlying filesystem and information concerning an underlying physical drive. The example method additionally includes freezing the application instance in response to a first instruction, and then thawing the application instance in response to a second instruction.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the

Abstract: A method of erasing a cloud host in a cloud-computing environment includes: receiving a cloud host secure erasing request; generating an erase instruction according to the request; and sending the erase instruction to a secure erasing server, such that the secure erasing server calls a secure erasing daemon process on the corresponding host machine according to the erase instruction, and erases the cloud host to be erased on the host machine via the secure erasing daemon process.

Abstract: A data writing method, a memory storage device and a memory control circuit unit are provided. The data writing method includes: writing first data belonging to a first logical sub-unit of a first logical unit and second data belonging to a second logical sub-unit of the first logical unit to a first physical erasing unit and a second physical erasing unit respectively; recording use information corresponding to each logical unit; and executing a data arrangement operation corresponding to the first logical unit based on the use information of the first logical unit to copy the first data and the second data from the first physical erasing unit and the second physical erasing unit to a third physical erasing unit, wherein a logical address range of the second logical sub-unit follows a logical address range of the first logical sub-unit.

Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

Abstract: A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric and a health-based adjustment of the invalidation metric. The controller selects a garbage collection unit on which to perform garbage collection from among a plurality of garbage collections units predominately based on the invalidation metric for the garbage collection unit and also based on the health-based adjustment for the garbage collection unit. In response to selection of the garbage collection unit, the controller performing garbage collection for the garbage collection unit.

Abstract: Deduplication of virtual-machine disk images and other disk images can involve identifying the first clusters in a file. The clusters are hashed. The first-in-file hashes (generated from first-in-file clusters) are stored in an in-memory index, while the full set of hashes is streamed in order to find matches with the hashes stored in the in-memory index. First-in-file hashes in the stream are compared, while other hashes in the stream are compared only if the immediately preceding hash resulted in a match. Comparing non-first-in-file hashes requires disk accesses, but since such comparisons are conditioned on first-in-file matches, there are relatively likely to result in sequences of matches. The net effect is a relatively fast deduplication with compression approaching that resulting from a full comparison of all hashes.

Abstract: Encoding a file into a plurality of chunks, wherein a subset of the plurality of chunks may be used to create a functional equivalent of the file. At least one additional chunk is created from the plurality of chunks. The at least one additional chunk is directed to be stored in a cache memory and the plurality of chunks are directed to be stored on at least one storage node. Upon demand for the file, at least one additional chunk is cased to be retrieved from the cache and at least a portion of the plurality of chunks are caused to be retrieved from the at least one storage node and the functional equivalent of the file is constructed through utilization of the at least one additional chunk and the portion of the plurality of chunks.