Abstract: A system comprising integrated circuit (IC) dice having memory cells and a processing device coupled to the IC dice. The processing device to perform operations including: intercepting an input/output (IO) write request directed at the IC dice; causing a device mapping logic to enter an initial state associated with a first group of memory cells of the IC dice; caching a write pointer that includes a location within the first group of memory cells; transitioning the device mapping logic from the initial state to a sequential IO state; and, in response to determining the IO write request is directed to the location of the write pointer, causing data associated with the IO write request to be sequentially written to IC dice starting at the location of the write pointer.

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the non-volatile memory device.

Abstract: A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes monitoring I/O to multiple volumes residing on a storage system. The storage system includes a cache to store data associated with the volumes. The method determines, from the I/O, which particular volumes of the multiple volumes would benefit the most if provided favored status in the cache. The favored status provides increased residency time in the cache to the particular volumes compared to volumes not having the favored status. The method generates a list of the particular volumes and transmits the list to the storage system. The storage system, in turn, provides increased residency time to the particular volumes in accordance with their favored status. A corresponding system and computer program product are also disclosed.

Abstract: During a power-on self-test (POST), the BIOS of an information handling system may read a percentage remaining of a persistent memory device. If the percentage remaining satisfies a threshold, the BIOS may provide a message recommending that the persistent memory device be replaced, or automatically swapping the namespaces between two sets of persistent memory devices based on the write endurance remaining threshold.

Abstract: Embodiments of the present disclosure provide a protective apparatus for an indirect access memory controller. The apparatus can include: a bus monitoring unit configured to monitor a bus address and detect an operation type of a bus accessing the indirect access memory controller, update a corresponding window register if the operation type is a window register operation, initiate permission authentication if the operation type is a register controlling operation, and perform list entry configuration if the operation type is a permission list configuration operation; a window register unit configured to store operation addresses of different access types; a permission list unit configured to partition a memory space into several virtual memory protection areas, and independently set a access permission attribute for each memory area; and an unauthorized operation processing unit configured to process a subsequent operation performed when a permission violating access occurs.

Abstract: An archival data storage service identifies, in response to a request to retrieve data previously archived by the service, a set of data storage devices that collectively include the data. From the set of data storage devices, the archival data storage service identifies a set of bins, where a subset of the set of bins includes the data. Based on a deadline for fulfillment of the request, the archival data storage service generates a schedule for retrieval of the set of bins for obtaining the data. The schedule is provided to cause retrieval of the set of bins in accordance with the schedule.

Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. Circuitry is configured to relocate the data of the first portion that is associated with one of the first number of logical block addresses to one of the two physical blocks of cells that don't have data stored therein, and relocate the data of the second portion that is associated with one of the second number of logical block addresses to the other one of the two physical blocks of cells that don't have data stored therein.

Abstract: A data storage system includes multiple head nodes and data storage sleds. Volume data is replicated between a primary and one or more secondary head nodes for a volume partition and is further flushed to a set of mass storage devices of the data storage sleds. Volume metadata is maintained in a primary and one or more secondary head nodes for a volume partition and is updated in response to volume data being flushed to the data storage sleds. Also, the primary and secondary head nodes store check-points of volume metadata to the data storage sleds, wherein in response to a failure of a primary or secondary head node for a volume partition, a replacement secondary head node for the volume partition recreates a secondary replica for the volume partition based, at least in part, on a stored volume metadata checkpoint.

Abstract: A system for monitoring a plurality of storage systems includes an interface specifying a set of methods for using at least one storage system, an implementation of the interface for each of the plurality of storage systems, wherein at least one of the implementations of the interface is configured to process a plurality of requests, and a performance monitor configured to monitor performance of requests for at least one of a plurality of classes of requests.

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Disclosed herein is an apparatus and method for a naming service in a distributed memory object system. In one embodiment, a name service method includes electing a primary node for the master key value store from a plurality of name service nodes, the primary node to receive master key value requests, a master key value store containing an entry for each directory within the distributed memory object, wherein the master key value store is configured for associating a directory pathname to a uniform unique identifier, and replicating the master key value store across the plurality of name service nodes.

Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.

Abstract: The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.

Abstract: A method for managing backups includes obtaining a plurality of parameters for a data item, filtering the plurality of parameters to obtain a plurality of filtered parameters, evaluating each filtered parameter of the plurality of filtered parameters to obtain a plurality of evaluated parameters, updating a promotion parameter register based on the plurality of evaluated parameters, and processing a backup request using the promotion parameter register, wherein the backup request specifies the data item.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: The disclosed technology provides a method that improves CCT in SMR device systems. In one implementation, the method comprises writing data to a shingled magnetic recording (SMR) band in a storage device, determining whether an off-track write has occurred, identifying unsafe written data in response to determining that an off-track write has occurred, determining whether caching space is available upon identifying unsafe written data, continue writing data to the SMR band without a write retry upon determining that caching space is available, and writing unsafe written data to the available caching space. In another implementation, the method comprises receiving a request to repair an encroached track in an SMR band, recovering encroached data to a dynamic random-access memory, determining whether caching space is available, writing the recovered data to the available caching space upon determining that caching space is available, and merging other cached data in the SMR band.

Abstract: Disclosed herein is an apparatus and method for a distributed memory object system.