Abstract: A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.

Abstract: Examples of the presently disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Specifically designed around the structure and operation of aCAM arrays, these circuits include counter sub-circuits electrically connected to match lines of aCAM rows such that the counter sub-circuits receive match-related signals output from aCAM rows. The value stored by a counter sub-circuit may change in response to receiving a match signal, and may remain the same in response to receiving a mismatch signal. As will be described in greater detail below, the stored value of the counter sub-circuit may be used to detect/identify an error in its associated aCAM row after a set of (specially-computed) error-detection input vectors are sequentially applied to the circuit.

Abstract: A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node V2C message. The method stores, in a check node unit CNU memory, check information associated with the calculated V2C message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.

Abstract: Systems and methods for testing components or scenarios with execution history are disclosed. A method may include: receiving, at a testing interface and from an application or program executed by a user electronic device, an identification of a test and one or more data layers of a plurality of data layers in pod to test, the plurality of data layers including a data collection layer, a data ingestion layer, a data messaging layer, a data enrichment layer, and a data connect layer; receiving, by the testing interface, a selection of testing parameters or values for the identified test; retrieving, by the testing interface, the identified test; executing, by the testing interface, the identified test on the identified one or more data layers using the selected testing parameters or values; retrieving, by testing interface, results of the execution of the test; and outputting, by the testing interface, the results.

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

Abstract: There is provided methods and processors for executing Forward Error Correction (FEC) coding. The method includes acquiring a stream of real data symbols from a communication medium. The stream of real data symbols being arranged in a real matrix. The method includes generating virtual data symbols being arranged in a virtual matrix. The generating includes applying an interleaver map onto the matrix such that (i) at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of (ii) real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1. The method includes decoding codewords formed by the virtual matrix and the matrix.

Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: In a wireless local area network (WLAN) system, a transmission STA can transmit a PPDU via a 320 MHz channel, and a Medium Access Control (MAC) signal may be generated for the PPDU. The MAC signal may include puncturing pattern information and channel center frequency segment (CCFS) information for a 320 MHz band. The CCFS information may include a first CCFS field related to channel center frequency (CCF) information of a primary 160 MHz channel, and a second CCFS field related to CCF information of a 320 MHz channel.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Abstract: A method for processing an image frame includes: obtaining an image frame to be displayed; determining whether pixel data in the image frame to be displayed is lost; and using preset replacement data as data of target pixels in the image frame to be displayed, in response to determining that the pixel data in the image frame to be displayed is lost.

Abstract: Embodiments of this application disclose a data processing method, an apparatus, and a device. The data processing method may be performed by a first communication device, and the first communication device is a transmit end of encoded data. During each time of transmission, the first communication device places information bits into code blocks according to a specified order.

Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.

Abstract: A user equipment (UE) may transmit, to a network node, an indication of support for a decoder success prediction capability. The network node may obtain the indication of support by the UE for the decoder success prediction probability. The network node may output a transmission for the UE including one or more parameters based on the indication of support by the UE for the decoder success prediction capability. The UE may receive the transmission including one or more code blocks based on the indication of support for the decoder success prediction capability. The network node may optimize a multiple incremental redundancy scheme (MIRS) schedule for at least one of transmitting the transmission or retransmitting the transmission based on the indication of support by the UE for the decoder success prediction capability. The transmission may include the MIRS schedule.

Abstract: The disclosure provides a semiconductor storage element which is provided with an error detection and correction circuit and, when an uncorrectable error occurs in the semiconductor storage element, capable of promptly transferring the occurrence to the outside, and provides a semiconductor storage device and a system-on-chip using the same. The semiconductor storage element includes a storage part storing data, an error detection and correction part detecting an error in the data stored in the storage part and correcting the error if possible, a monitoring part issuing an uncorrectable error signal when an uncorrectable error occurs in the error detection and correction part, and a terminal transmitting the uncorrectable error signal to the outside.

Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.

Abstract: A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

Abstract: In an audio apparatus including a first device and a second device that each receive the same audio data transmitted from a source device, a device having the worse reception environment of the audio data out of the first device and the second device, operates as a primary device that performs a retransmission request for the audio data to the source device, and a device having the better reception environment operates as a secondary device that performs the retransmission request for the audio data to the primary device.

Abstract: A communication method includes executing a cyclic block permutation for a codeword generated based on a quasi-cyclic parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the cyclic block permutation is permutation of cyclic blocks within the codeword, and mapping each bit of the codeword for which the cyclic block permutation is executed to any one of constellation point of a non-uniform constellation.