Abstract: A polar code decoding apparatus according to an embodiment includes a divider configured to generate a decoding tree in which a plurality of nodes including one or more critical sets for a polar-encoded codeword are formed in a hierarchical structure, and divide the decoding tree into one or more partitions, each partition equally including lowest nodes of the decoding tree, a determiner configured to determine a memory size for storing a primary decoding result based on a specific partition, the specific partition being selected from among the one or more partitions based on the number of critical sets included in each partition, and a decoder configured to decode the codeword primarily by using a successive cancellation (SC) decoding technique.

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

Abstract: Systems and processes for training and compressing a convolutional neural network model include the use of quantization and layer fusion. Quantized training data is passed through a convolutional layer of a neural network model to generate convolutional results during a first iteration of training the neural network model. The convolutional results are passed through a batch normalization layer of the neural network model to update normalization parameters of the batch normalization layer. The convolutional layer is fused with the batch normalization layer to generate a first fused layer and the fused parameters of the fused layer are quantized. The quantized training data is passed through the fused layer using the quantized fused parameters to generate output data, which may be quantized for a subsequent layer in the training iteration.

Abstract: The present application concerns an iterative bit-flipping decoding method using symbol or bit reliabilities, which is a variation of GRAND decoding and is denoted by ordered reliability bits GRAND (ORBGRAND). It comprises receiving a plurality of demodulated symbols from a noisy transmission channel; and receiving for the plurality of demodulated symbols, information indicating a ranked order of reliability of at least the most unreliable information contained within the plurality of demodulated symbols. A sequence of putative noise patterns from a most likely pattern of noise affecting the plurality of symbols through one or more successively less likely noise patterns is provided.

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Abstract: One example method includes obtaining L1 first decoding paths of an (i?1)th group of to-be-decoded bits, where i is an integer, received data corresponds to P groups of to-be-decoded bits, and 1<i?P, determining at least one second decoding path corresponding to each first decoding path, where a quantity of second decoding paths corresponding to each first decoding path is less than 2n, and where n is a quantity of information bits included in an ith group of to-be-decoded bits, and determining at least one reserved decoding path of the ith group of to-be-decoded bits in second decoding paths corresponding to the L1 first decoding paths. The at least one reserved decoding path includes a decoding result of the ith group of to-be-decoded bits.

Abstract: Provided are a memory controller with improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes an error correction code (ECC) circuit configured to perform an error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip from among a plurality of memory chips as an indicator chip, monitor an error occurrence in the indicator chip based on a result of the error detection, and output reliability deterioration information indicating that the reliability of the memory device is deteriorated based on a result of the monitoring.

Abstract: A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

Abstract: An improved method for investigating a functional behavior of a component of a technical installation includes comparing a signal of the component to be investigated and representing the functional behavior of the component with a reference signal which describes an average functional behavior of identical components. During the comparison, a comparison variable describing the deviation of the signal from the reference signal is determined. In addition, a probability of the occurrence of the comparison variable is determined by using a predefinable distribution of a multiplicity of such comparative variables. A computer program and a computer readable storage medium are also provided.

Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.

Abstract: Proposed is a method for a terminal to decode a signal. In particular, the method for a terminal to decode a signal comprises: a step for demodulating a first low density parity check (LDPC)-coded signal; and a step for decoding a second signal obtained from the first demodulated signal through a trained neural network. The second signal is obtained by using: an output sequence generated on the basis of the trained neural network; and a log likelihood ratio (LLR) sequence of the first signal.

Abstract: Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

Abstract: This application provides a data transmission method, a base station, and a terminal device. The method includes: determining, by a base station, a target base graph in N Raptor-like LDPC base graphs; and sending, by the base station, indication information to a terminal device, where the indication information is used to indicate the terminal device to use the target base graph to perform LDPC encoding and decoding. Based on the foregoing technical solution, the base station may determine a target base graph in a plurality of Raptor-like LDPC base graphs that may be used to perform LDPC encoding and decoding, and indicate the target base graph to the terminal device. Further, for one code rate or one code length, the base station may select different base graphs as required.

Abstract: An electronic circuit comprising an SRAM memory, a control unit, an error detection and correction module and a scrubbing module. The electronic circuit further comprises an integrated SEU monitor of the SRAM memory. The SEU monitor does not use standalone or specialized SRAM memories or particle detectors. Rather, the same SRAM memory that is used for the main operation as a storage element of the electronic circuit serves simultaneously as detector for the SEU monitor. The proposed SEU monitor enables real-time monitoring of the SEU rate in order to detect early the high radiation levels and apply appropriate hardening measures. Furthermore, a method for monitoring an SEU rate and determining permanent faults in an electronic circuit is suggested.

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Abstract: One example method includes accessing I/O traces, generating parameters based on the I/O traces, and defining an autoencoder deep neural network, training the autoencoder deep neural network using the parameters, collecting and storing new I/O traces, computing an encoded features difference series using the new I/O traces, detecting breakpoints in the encoded features difference series, evaluating a utility of the breakpoints, and performing an action based on the breakpoint utility evaluation.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.