Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.

Abstract: A communication method includes executing a cyclic block permutation for a codeword generated based on a quasi-cyclic parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the cyclic block permutation is permutation of cyclic blocks within the codeword, and mapping each bit of the codeword for which the cyclic block permutation is executed to any one of constellation point of a non-uniform constellation.

Abstract: In an audio apparatus including a first device and a second device that each receive the same audio data transmitted from a source device, a device having the worse reception environment of the audio data out of the first device and the second device, operates as a primary device that performs a retransmission request for the audio data to the source device, and a device having the better reception environment operates as a secondary device that performs the retransmission request for the audio data to the primary device.

Abstract: A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

Abstract: A computer-implemented method for decoding syndromes of a quantum error correction code, the syndromes comprising measurement data from a quantum computer, the method comprising: receiving syndrome measurement data comprising a plurality of quantum error correction rounds performed on a plurality of qubits; identifying a plurality of non-overlapping first blocks within the syndrome measurement data, wherein: each first block has: a first central block of quantum error corrections rounds; and a first buffer block of quantum error correction rounds, wherein the first buffer block surrounds the first central block, and each first block is surrounded by an interstitial region of quantum error correction rounds; identifying the location of a first set of errors in the plurality of qubits by decoding each first block to provide respective decoded first central blocks and respective decoded first buffer blocks; outputting the location of the first set of errors contained within each decoded first central block.

Abstract: Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received from a memory device. One or more of the plurality of bits in the codeword are flipped in each of a plurality of error correction iterations. Each bit is flipped using a first bit flipping criterion that includes comparing a first bit flipping threshold and an energy function of each bit. Responsive to the determining an iteration count threshold is satisfied and a parity violation count threshold is satisfied, one or more of the plurality of bits in the codeword are flipped using a second bit flipping criterion for one or more error correction iterations. The second bit flipping criterion differs from the first bit flipping criterion.

Abstract: An audio packet loss concealment method, an audio packet loss concealment device and a Bluetooth receiver are described. The audio packet loss concealment method comprises: determining whether each data packet divided into a plurality of frequency bins in a frequency domain is correct after audio data is transformed from a time domain to the frequency domain; classifying the frequency bins in the incorrect data packet into a first set of frequency bins and a second set of frequency bins; and recovering data in the first set of frequency bins by a GAPES algorithm, and recovering data in the second set of frequency bins by a predefined algorithm, wherein the predefined algorithm involves far less computation when compared with the GAPES algorithm.

Abstract: This application provides encoding and decoding methods to reduce retransmission in satellite communication. A sending apparatus obtains an information transport block, where the information transport block includes a plurality of code blocks; and generates a redundant code block based on at least two of the plurality of code blocks. The at least two code blocks and the redundant code block are sent over a satellite channel after channel coding. A receiving apparatus receives the to-be-decoded information over the satellite channel, calculates, based on the to-be-decoded information of the at least two code blocks and the redundant code block, an a priori log-likelihood ratio of a to-be-decoded bit, and combines the a priori log-likelihood ratio and a log-likelihood ratio obtained after demodulation, to obtain a diversity gain. Decoding is performed based on the combined log-likelihood ratio. This method improves decoding accuracy and reduces the need for retransmission.

Abstract: A team polar decoder (TPD) includes polar decoders (PPDs) connected to a channel, and a team decision maker (TDM) connected to the PPDs and a destination. Component polar decoders (CPDs) decode a polar code in accordance with a polar code. Each CPD receives a noisy code block (NCB) from the channel, and decodes the NCB in consecutive steps to obtain a decoded transform input block (DTIB). Each CPD is generates, at an end of the decoding step, a candidate decoded data block from the DTIB by a data-demapping operation that is an inverse of a data-mapping operation applied at a polar encoder, then sends the CDDB to the TDM, which receives the CDDBs from the PPDs, generates a decoded data block (DDB), and sends the DDB to the destination.

Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.

Abstract: This application discloses a polar code encoding method and apparatus, which can improve encoding performance through codeword construction. The method includes: obtaining K information bits to be encoded, where K is a positive integer; determining a first bit sequence based on the K information bits to be encoded, where a length of the first bit sequence is N, the first bit sequence includes fixed bits and the K information bits to be encoded, and the K information bits to be encoded may further include a check bit; determining a second bit sequence based on the first bit sequence and an upper triangular matrix, where the upper triangular matrix is a matrix having N rows and N columns, and the upper triangular matrix may be an upper triangular Toeplitz matrix; and performing polar code encoding on the second bit sequence to obtain and output an encoded sequence.

Abstract: An apparatus for wireless communication is provided. The apparatus may be a receiver device that includes an error correction decoder, such as a low-density parity check (LDPC) decoder. The apparatus may achieve power savings and/or operation cycle savings by disabling the error correction decoder in scenarios where bits of a codeword in a signal transmission are received without errors. The apparatus obtains a first set of bits of a codeword, wherein the codeword includes the first set of bits and a second set of bits, and wherein the second set of bits is punctured. The apparatus recovers the second set of bits based on at least the first set of bits and determines whether to operate an error correction decoder based on a result of an error detection operation performed on the codeword using the first set of bits and the second set of bits.

Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.

Abstract: In embodiments of the present disclosure, there is provided an approach for selecting a channel puncturing scheme based on channel qualities. A method comprises detecting channel interference between neighbor access points (APs), and determining whether a preamble puncturing needs to be enabled based on some puncturing conditions. After determining that a preamble puncturing needs to be enabled, scores for candidate puncturing patterns are calculated based on channel qualities of the sub-channels in the channel, and a proper puncturing pattern can be selected based on the respective scores. Embodiments of the present disclosure can help AP to achieve an effective and better puncturing scheme in real deployment.

Abstract: The invention relates to a communication apparatus comprising a processor part, and a data transfer part. The apparatus is configured to receive, by the data transfer part, a packet comprising a network identification code (NIC) of a communication apparatus that transmitted the packet. A header field of the packet comprises a first part of the NIC and a second part of the NIC is included in another field of the packet. The apparatus is further configured to define, by the processor part, that the received packet is from a network to which the communication apparatus belongs, if the first part of the NIC of the received packet corresponds to the first part of the NIC of said communication apparatus. The invention relates also to method for a communication apparatus, a communication system, a computer program, and a computer readable medium.

Abstract: A storage system, including a storage device configured to store a plurality of encoded values, wherein each value of the plurality of encoded values has a predetermined value length and is within a predetermined range, and wherein the predetermined range is not a power of 2; and at least one processor configured to: group the plurality of encoded values into a codeword; obtain a plurality of bit chunks, wherein each bit chunk of the plurality of bit chunks represents a corresponding encoded value of the plurality of encoded values, and wherein a length of the each bit chunk is selected from among one or more predetermined bit chunk lengths which are determined based on the predetermined range; select a variable-length prefix from among a plurality of variable-length prefixes, wherein the variable-length prefix indicates bit chunk lengths of the plurality of bit chunks; obtain a compressed codeword including the variable-length prefix and the plurality of bit chunks; and decode the plurality of encoded values

Abstract: The invention relates to a detection circuit, a detection method, an electronic device, and a computer-readable storage medium. The detection circuit includes: an error correction coding module configured to obtain data to be checked, and perform, based on an error correction coding logic, error correction coding on the data to be checked, to output target coded data; a data mask interface configured to receive comparison coded data, where the comparison coded data is associated with ideally coded data of the data to be checked; a comparison checking module configured to perform a checking comparison on the target coded data and the comparison coded data to output a checking comparison result; and a logic verification module configured to determine a coding verification result of the error correction coding module based on the checking comparison result. The comparison checking data verifies correctness of the error correction coding logic.

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.