Abstract: A method performed by one or more processors that preserves a machine learning model comprises accessing model parameters associated with a machine learning model. The model parameters are determined responsive to training the machine learning model. The method comprises generating a plurality of model parameter sets, where each of the plurality of model parameter sets comprises a separate portion of the set of model parameters. The method comprises determining one or more parity sets comprising values calculated from the plurality of model parameter sets. The method comprises distributing the plurality of model parameter sets and the one or more parity sets among a plurality of computing devices, where each of the plurality of computing devices stores a model parameter set of the plurality of model parameter sets or a parity set of the one or more parity sets. The method comprises accessing, from the plurality of computing devices, a number of sets comprising model parameter sets and at least one parity set.

Abstract: A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1?k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

Abstract: A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

Abstract: The disclosure proposes a technique for achieving validity decision performance of a suitable level in communication and broadcasting systems using a polar code. The polar code is a channel code in which it is difficult to use a syndrome check due to a successive cancellation (SC)-based decoding operation and coding structure. Accordingly, in the communication of the related art and broadcasting systems using the polar code, a validity check of a decoding result has been performed by using a path-metric (PM) generated during decoding and a concatenated error detection code, such as a cyclic redundancy check (CRC) code. However, it is difficult to achieve target error detection performance only via such methods when the length of the CRC code is short or when input and output lengths of a code are short.

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

Abstract: The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

Abstract: A method for execution by an input/output (IO) control module of an integrated circuit (IC) includes determining whether a programmable IO interface module is for dynamic or static use. The programmable IO interface module includes a configurable front-end module and a configurable back-end module. When the programmable IO interface module is for the dynamic use, determining to configure the programmable IO interface module as the dynamic use of a configuration of a plurality of configurations. The plurality of configurations includes a bidirectional interface, an input, an output, a concurrent drive and sense interface, and a concurrent transmit-receive interface. The method further includes configuring the front-end module in accordance with the configuration, configuring the back-end module in accordance with the configuration, and determining whether to change the configuration to another configuration of the plurality of configurations.

Abstract: Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

Abstract: In some examples, a system groups a plurality of blocks of encoded data into first segments, each first segment comprising multiple blocks of the plurality of blocks, and the encoded data being based on application of erasure correction coding on input data. The system stores the first segments in respective failure domains of a first quantity of failure domains in a first erasure correction configuration, where the first erasure correction configuration enables error recovery in response to lost encoded data in a specified number of failure domains. The system changes from the first erasure correction configuration to a second erasure correction configuration by reorganizing the first segments into second segments, each second segment comprising a different quantity of blocks of encoded data than a first segment.

Abstract: Wireless devices may use polar codes for encoding transmissions and may support combining transmissions to improve decoding reliability (e.g., by achieving chase combining and incremental redundancy (IR) gains). For example, an encoding device may puncture a set of mother code bits using different puncturing patterns to obtain different redundancy versions for a first transmission and a re-transmission. Each puncturing pattern may correspond to an equivalent decoding performance. In some cases, to obtain equivalent puncture sets, the encoding device may perform punctured index manipulation procedures on an initial puncturing pattern. A punctured index manipulation procedure may involve switching a binary state for a binary bit at a same binary bit index for each puncture index in a puncturing pattern. A device may receive the transmissions generated using the equivalent puncture sets and may combine the information for improved decoding reliability.

Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.

Abstract: A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and energy function values are determined for bits of the codeword. A bit flipping criterion is selected using the syndrome information from a plurality of values. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies the bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

Abstract: This disclosure provides systems, methods and apparatus, including computer storage media, for retransmission of sidelink transmissions using network coding with binned feedback. A transmitting device transmits a transport block and a request for a network coding (NC) encoding device to retransmit the transport block to a plurality of user equipment (UEs). The UEs decode the transport block and report an acknowledgment (ACK) or negative acknowledgment (NACK) on a physical sidelink feedback channel (PSFCH) resource associated with a bin for the UEs. The NC encoding device decodes the PSFCH resource for each bin to determine an ACK or NACK status for each bin, and determines whether to encode the transport block in a NC combination packet. The UEs receive the NC combination packet including an encoding of a subset of transport blocks. The receiving devices transmit an ACK or NACK on a PSFCH resource for a bin for each transport block.

Abstract: A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.

Abstract: A method and system for LDPC decoding method. In the method and system, an LDPC codeword is decoded using a quasi-cyclic matrix. A first message for variable nodes in a circulant column of the quasi-cyclic matrix and a second message for check nodes belonging to the circulant column are computed. Parity and syndrome are computed using the computed first and second messages. A bit error rate is calculated for both a first mode with no error in a parity portion of a codeword and a second mode with errors in the parity portion of the codeword.

Abstract: Methods, systems, and devices for post error correction code (ECC) registers for cache metadata are described. A device may read metadata from a memory array included in the device. The metadata may include information for operating a volatile memory as a cache for a non-volatile memory. The device may perform an ECC operation on the metadata based on reading the metadata from the memory array. After performing the ECC operation on the metadata, the device may write the metadata to a register that is coupled with the memory array. The device may then write the metadata from the register to the memory array.

Abstract: Systems and methods for improving the error floor performance in decoding generalized product codes (GPC) are described. The systems and methods can implement a two stage process to decode a GPC block code and break a stall error pattern for the decoding the block code. In the first stage, erroneuous bits in a codeword can be flagged. In the second stage, some of these bits and related bits in a codeword can be toggled to generate one or more test patterns. The test patterns can be decoded and one of them can be selected using a particular selection criteria to ultimately break the stall error pattern and improve the error floor performance.

Abstract: A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.