Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Abstract: A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group.

Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

Abstract: Provided is an optical transmission device including: a symbol demapping unit; a likelihood generation circuit configured to generate likelihoods relating to the reception signal; and an error correction decoding unit configured to execute soft decision decoding. The likelihood generation circuit includes: a first one-dimensional-modulation lookup table configured to input the signal of the I-axis component as an argument to output a first likelihood; a second one-dimensional-modulation lookup table configured to input the signal of the Q-axis component as an argument to output a second likelihood; and a two-dimensional-modulation lookup table configured to input, as an argument, the signal being the concatenation of the signal of the I-axis component and the signal of the Q-axis component, to generate a third likelihood. The error correction decoding unit is configured to execute the soft decision decoding based on the first likelihood, the second likelihood, and the third likelihood.

Abstract: A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate Pe0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximal subset of a current solution, and calculating a new bit error rate Penew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate Pe0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.

Abstract: Embodiments are directed to error resistant logging. A write-ahead log (WAL) for preserving a verifiable record of file system activity may be provided such that the WAL may include a sequence of log blocks that each may include a cyclic redundancy check (CRC) value of a next adjacent log block in the WAL. In response to executing a file system operation associated with payload data, further actions may be performed, including: generating log blocks based on the payload data; generating a log segment that includes the log blocks; modifying a portion of the contents of a head-block of the log segment such that the modified head-block of the log segment has a CRC value that matches a CRC value of a tail-block of the WAL; copying the contents of the modified head-block of the log segment into the tail-block of the WAL.

Abstract: An error rate measuring apparatus that measures whether or not an FEC operation of the device under test is possible based on a comparison result of the signal received from the device under test and a test signal includes an operation unit that sets a codeword length and an FEC symbol length of the FEC corresponding to a communication standard of the device under test, a data comparison unit that compares bit string data obtained by converting the signal received from the device under test with error data to detect an FEC symbol error of each FEC symbol length, a display unit that associates the bit string data of the FEC symbol length as one point with one unit region of a display region and performs color-coding display depending on presence or absence of occurrence of the FEC symbol error by each FEC symbol length.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

Abstract: Various embodiments described herein provide for a mechanism for detecting failure in the operation of FEC of a physical layer device, such as a physical layer device of a networking application that seeks to meet a functional safety standard (e.g., ISO 26262). In particular, some embodiments described herein provide one of several methods for detecting a failure in the operation of a FEC decoder of a physical layer device.

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

Abstract: Provided is a 5th generation (5G) or 6th generation (6G) communication system for supporting higher data rates after 4G communication systems such as long term evolution (LTE). A communication method of a user equipment (UE) includes receiving, from a base station (BS), information about a decoding mode including bit information corresponding to the number of times of perturbation, receiving data from the BS on a Physical Downlink Shared Channel (PDSCH), and decoding the received data based on the information about the decoding mode, wherein the information about the decoding mode may be generated based on service information including at least one of Quality of Service (QoS), a service priority, packet delay performance, packet error probability performance, a requirement, or a data transmission scheme.

Abstract: Methods, systems, and devices for wireless communications are described. A communication device, otherwise known as a user equipment (UE) or a base station may select a sequence from a set of sequences for conveying a payload including a set of bits. A length of the selected sequence may be based on a number of time periods for conveying the payload and a number of frequency tones for conveying the payload. The communication device may apply an interleaving function to the selected sequence to generate an interleaved sequence, and transmit the payload including the set of bits using the interleaved sequence. Likewise, the communication device may receive the payload including the set of bits using an interleaved sequence, and apply an interleaving function to de-interleave the interleaved sequence to generate a selected sequence. The communication device may thereby decode the payload based on the selected sequence.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.

Abstract: Methods and apparatus are provided for controlling wireless signal transmissions, wherein problematic symbol patterns are relocated to an erasure region of a data packet prior to erasure encoding and transmission. Relocating the problematic symbol patterns is done so that, when the resulting erasure codeword is punctured and transmitted, the problematic patterns are not transmitted. Yet, those patterns can be restored by the decoder at the receiving device using an erasure decoder in accordance with erasure decoding techniques, e.g., punctured low-density parity-check (LDPC) decoding techniques. In this manner, problematic symbol patterns that may be corrupting during transmission due to noise are removed (punctured) prior to transmission, then restored by the decoder during decoding.

Abstract: Provided is a storage system that performs inter-node movement of parity and reconfiguration of a stripe when a node configuration is changed. The storage system includes a plurality of nodes and a management unit, in which the nodes are targets for data write and read requests, form a stripe by a plurality of data stored in different nodes and parity generated based on the plurality of data, and store the parity of the stripe to which the data under the write request belongs in a node different from the plurality of nodes that store the plurality of data so as to perform redundancy; and the management unit transmits, to the node, an arrangement change request to perform the inter-node movement of the parity and the reconfiguration of the stripe when the node configuration is changed.

Abstract: Methods, devices, and systems related to memory device on-die ECC data are described. In an example, a scrub operation can be performed on data in order to determine which rows of memory cells in an array include a particular number of errors. The particular number of errors can be a number of errors that exceed a threshold number of errors. An address of the determined rows with the particular number of errors can be stored in memory cells of the array for later access. The address of the determined rows can be accessed to perform a user-initiated repair operation, a self-repair operation, a refresh operation, and/or to alter timing of access of the cells or alter voltage of the cells.