Abstract: A scanning probe microscope is used to fabricate a gate or other feature of a transistor by scanning a silicon substrate in which the transistor is to be formed. An electric field is created between the cantilever tip and the silicon substrate, thereby causing an oxide layer to be formed on the surface of the substrate. As the tip is scanned across the substrate the electric field is switched on and off so that an oxide pattern is formed on the silicon. Preferably, the oxide pattern is formed on a deposited layer of amorphous silicon. Extremely small features, e.g., a MOSFET gate having a length of 0.2 .mu.m or less can be fabricated by this technique.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

Abstract: A method wherein an IC component is mounted to electrodes provided in a transparent portion of a flat panel display with interposition of an anisotropic conductive adhesive or film, includes steps of detecting, when mounting the IC component onto the transparent portion of the flat panel display for temporary bonding to the adhesive or film, positional displacement amounts of first positional alignment portions in two positions of the mounted IC component relative to second positional alignment portions in two positions of the transparent portion of the flat panel display in correspondence with the first positional alignment portions by a camera from a side of the flat panel display opposite from a side on which the IC component is mounted, thereby inspecting positional alignment state of bumps of the IC component with the electrodes of the flat panel display, feeding back the positional displacement amount of the IC component with respect to the flat panel display when the positional alignment state is not a

Abstract: A metallization system (19) for a semiconductor component (20) includes depositing a dielectric layer (12) over a substrate (10), etching a via (14) in the dielectric layer (12), sputtering a metal layer (17) of aluminum, copper, and tungsten over the dielectric layer (12) and in the via (14), and sputtering a different metal layer (18) of aluminum and copper over the first metal layer (17) and in the via (14). The metallization system (19) reduces the reliability issues associated with electromigration and stress migration while enhancing the ability to fill vias with large aspect ratios.

Abstract: A method for fabricating a semiconductor device of the invention, the method includes the steps of: providing an oxygen concentration in a region of a silicon film of 1.times.10.sup.18 cm.sup.3 or less; depositing a film including a metal on the silicon film; and reacting the silicon film with the film including a metal so as to form a metal silicide film in the region of the silicon film.

Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.

Abstract: In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonuniformity during gate electrode etching. In this invention, a thin polysilicon layer is formed on the gate dielectric (gate oxide) layer and a thin oxide layer (not gate oxide) is formed on the thin polysilicon layer. The thin oxide layer (not gate oxide) is then patterned and etched to expose portions of the thin polysilicon layer. A thick polysilicon layer used to form the gate electrode is subsequently deposited. The thick polysilicon layer contacts the exposed portion of the underlying thin polysilicon layer, but is otherwise separated from the thin polysilicon layer by the thin oxide. The thin polysilicon layer is patterned and etched using a plasma etching process. The thin oxide (not the gate oxide) acts as an etching stop.

Abstract: Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure.

Abstract: An improved integrated circuit interconnection for interconnecting at least two conductive regions within an integrated circuit, and method for producing the same. The interconnection includes a tungsten layer and a barrier layer to provide a low contact resistance within the interconnection and between the conductive regions and the interconnection. The interconnection also includes an aluminum layer for providing a low sheet resistance in the current path between the two conductive regions. Thus the invention combines the advantages of an all tungsten interconnection with those of a tungsten capsuled aluminum interconnection.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Abstract: A method of forming an MOS gate includes providing a silicon substrate having a gate oxide formed thereon, forming a polysilicon layer on the gate oxide, defining a gate area including forming an oxide mask by positioning a light mask adjacent a surface of the polysilicon layer and exposing the surface through the light mask to a deep ultra violet light in an ambient containing oxygen. A layer of metal is deposited and annealed to form a silicide only where the layer of metal and polysilicon layer are in contact. The remaining metal layer and mask are removed, using the silicide as a mask, wherein the remaining polysilicon and the silicide form an MOS gate. Sidewall spacers are formed on opposing sides of the MOS gate and used in forming self aligned source and drain regions.

Abstract: Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure.

Abstract: An improved contact hole plug and method are disclosed, the plug connecting a first conductive layer to a second conductive layer which is insulated from the first conductive layer. The contact hole plug may be formed using the steps of: (1) forming a first conductive layer consisting of a multi-layer metal (2) forming an inter-layer insulating film, and a contact hole therein; and (3) carrying out a rapid heat treatment which causes an alloy reaction in the multi-layer metal, and the resulting alloy expands to form a plug in the contact hole. The rapid heat treatment may be accomplished with a heat treatment furnace or a rapid thermal annealing (RTA) process at a temperature of 300.degree.-600.degree. C. for about 30 seconds (RTA) or 30 minutes (heating furnace).

Abstract: A composite containing an integrated circuit chip having conductive site thereon and electrically conductive leads that are interconnected to the conductive site by electrically conductive wire; wherein the wire is coated with a dielectric material. Also, a method for fabricating the composite is provided.

Abstract: A method of processing a substrate, such as a semiconductor wafer, in a vacuum processing chamber includes the steps of depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases by flowing SiH.sub.4 into the chamber. Preferably, WSi.sub.x is deposited on a semiconductor wafer using a mixture comprising WF.sub.6, dichlorosilane and a noble gas, and the chamber is subsequently purged of residual WF.sub.6 and dichlorosilane by flowing SiH.sub.4 into the chamber. A further method of processing a substrate in a vacuum processing chamber includes the step of conditioning the chamber by flowing SiH.sub.4 into the chamber prior to depositing a material on the surface of the substrate. Semiconductor wafers processed according to the inventive method are characterized by more uniform sheet resistance values and reduced film stress.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A method for manufacturing semiconductor device having conductive metal leads 14 with improved reliability, and device for same, comprising conductive metal leads 14 on a substrate 12, a first insulating material 18 at least between the conductive metal leads 14, and dummy leads 16 proximate the conductive metal leads 14. Heat from the conductive metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The first insulating material 18 has a dielectric constant of less than 3.5. An optional heatsink 22 may be formed in contact with the first dummy leads 16 to further dissipate the Joule's heat from the conductive metal leads 14. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.