Abstract: A method for fabricating an integrated circuit device includes the steps of forming an insulating layer on a substrate and forming a plurality of parallel conductive lines on the insulating layer. An etch barrier is formed on each of the parallel conductive lines, and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and etching exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also discussed.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: An improved method for making a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits is achieved. The method involves forming metal lines on which is deposited a conformal PECVD oxide. A multilayer of spin-on glass, composed of at least four layers, is deposited and baked at elevated temperatures and long times after each layer to minimize the poisoned via problem on product with minimum feature sizes greater than 0.35 um. A multilayer of a low dielectric constant polymer can also be used to reduce the RC time delay on product having minimum feature sizes less than 0.35 um. After depositing a SiO.sub.2 on the SOG, or depositing a Fluorine-doped Silicon Glass (FSG) on the low k polymer, the layer is partially chemical/mechanically polished to provide the desired more global planar IMD. This eliminates the necessity of polishing back the SOG or polymer, which is difficult to achieve with the current technologies.

Abstract: The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer.

Abstract: The present invention is directed to a method for inhibiting silicon oxidation on a silicon surface by forming a very thin carbon-containing silicon surface layer on the silicon. The silicon surface is exposed to a carbon-containing plasma to form the carbon-containing silicon layer. The carbon treatment also renders he silicon surface slightly amorphous due to ion bombardments from plasma. An oxide free and slightly amorphous silicon surface promotes homogeneous progress of silicidation reaction between the silicon and a metal deposited thereon, which enables thin but smooth and stable silicide film formation. The present invention is also directed to a method for forming uniform silicon layers only on horizontal portions of features on a substrate. A silicon layer is deposited on to conform to all exposed surfaces of a device. The horizontal surfaces are then exposed to a carbon-containing plasma to form anti-oxidation layers on the horizontal surfaces.

Abstract: A solid electrolytic capacitor free of short circuits which may be caused by the creeping of a solid electrolyte comprising a conducting polymer, and having high volume efficiency per volume. The solid electrolytic capacitor is constructed by successively forming an oxide film, a solid electrolyte (conducting polymer) and a cathode layer on an anode body which has an anode lead planted thereon. Then heating is applied, by a heater chip, to a part of the solid electrolyte that has crept from the head of the anode body along the anode lead to convert it is insulation, so as to produce a solid electrolyte insulated portion thereby. Or, in another way, the creeping solid electrolyte can be removed by heating with a heater chip and generating a thermal decomposition reaction thereof while supplying sufficient additional oxygen.

Abstract: The invention provide a method for manufacturing a wire by etching a metallic film involving a high melting point metal without side etching. When a tungsten film 4c is etched by a mixed gas involving SF.sub.6 and N.sub.2, tungsten nitride films 14 are formed on side walls of an tungsten film 4c being etched, and said tungsten nitride films 14 serve as protector against etching. The selected figure is FIG. 5.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: After a contact hole is formed in an insulating film covering the surface of a semiconductor substrate, a Ti layer and a TiON (or TiN) layer are sequentially formed on the insulating film. On the TiON layer an Al alloy layer 18 containing Si is formed, and a reflow thermal treatment is performed after or during the formation of the Al alloy layer in order to improve step coverage. During this thermal treatment, Si nodules are generated. After a Ti layer is formed on the reflowed Al alloy layer, an annealing thermal treatment is performed for 120 seconds at a temperature of 450.degree. to 500.degree. C. With this thermal treatment, Si of Si nodules is absorbed in the Ti layer so that Si nodules are reduced or extinguished. After an antireflection TiN (or TiON) layer is formed on the Ti layer, wiring patterns are formed by using resist patterns as a mask. Since Si nodules are extinguished, wiring resistance can be reduced and an etching time can be shortened.

Abstract: A semiconductor device comprises at least one metal interconnect layer, a titanium-based barrier layer in contact with the metal interconnect layer. The metal interconnect layer contains titanium in an amount up to the limit of solid solubility at the peritectic temperature. The arrangement is effective to reduce hillock, spike, and notch formation in the semiconductor device.

Abstract: A method for metallizing semiconductor materials includes two processing steps. In the first step, a layer of an alloy of conductive metal, such as aluminum, and an Alloy Material such as hafnium, tantalum, magnesium, germanium, silicon, titanium, titanium nitride, tungsten and/or a composite of tungsten, is deposited on the surface in a single step from a single source. In the second step, a layer of the conductive metal is deposited over the alloy layer. Thus, using this method, metallization can be conveniently performed using two chambers.

Abstract: At least one of an interlayer insulating film is formed by fluorine contained silicon oxynitride which is obtained by chemical deposition growth process using fluoroalkoxysilane gas, nitrogen gas contained gas, and oxygen gas contained gas. The at least one-film is formed at a temperature of lower than 200.degree. C. As a result, reliability of a semiconductor device to be fabricated as described above is enhanced.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: The present invention relates to a method of depositing a platinum thin-film on a silicon wafer. The method includes the steps of depositing a platinum layer on an insulating oxide layer under an oxidation atmosphere to form a mixture film consisted of platinum grains, platinum oxide grains and oxygen adhered to those grains (hereinafter, "the mixture film" to be referred as "oxygen containing platinum thin-film"); depositing an additional platinum thin-film to a desired thickness on the oxygen containing platinum thin-film under a complete inert atmosphere; and annealing the silicon substrate at a temperature of 400.degree. to 1,300.degree. C. in order to remove oxygen present in the independent form or in platinum oxide form within the oxygen containing platinum thin-film and to stablize the entire platinum thin-film.

Abstract: This invention is a process for depositing tungsten metal on a silicon surface with the deposited layer having improved uniformity of thickness over prior art deposition techniques. The process involves the steps of removing any native silicon dioxide present on the silicon surface, forming a barrier layer which overlies the silicon surface which prevents the upward diffusion of silicon atoms from the polycrystalline surface, and depositing a final tungsten metal layer on top of the barrier layer. The barrier layer is preferably a refractory metal nitride. It may be formed directly by chemical vapor deposition, by reactive sputtering, or it may be formed indirectly by depositing a preliminary tungsten metal layer, subjecting the preliminary layer to a plasma formed from NH.sub.3 and N.sub.2 gases. Both preliminary and final tungsten metal layers are deposited preferably via chemical vapor deposition using the WF.sub.6 and SiH.sub.4 as reactants.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

Abstract: A method for forming an interconnect for a bare semiconductor is provided. The interconnect includes an insulating film with a pattern of conductors and microbumps adapted to make an electrical connection with contact locations on the die. The insulating film and conductors are mounted to a rigid substrate (e.g., silicon) using an lo elastomeric adhesive. The method includes forming conductive bus bars in electrical communication with the pattern of conductors to provide an electrical path for electroplating the microbumps onto the conductors. Following the electroplating step, the bus bars are severed and separate electrical paths are formed to the conductors. The bus bar can also be used in the completed interconnect to provide a common electrical path to select conductors. The interconnect can be used for testing the die or for providing a permanent electrical connection to the die.

Abstract: The present invention discloses a method for forming a tungsten silicide layer in a semiconductor device. A wafer to be deposited with a tungsten silicide layer is loaded into a chamber. The tungsten silicide layer is primarily deposited, thinner than desired in the device by a Chemical Vapor Deposition utilizing WF.sub.6 and SiH.sub.4 gases. The fluorine contained in the primarily deposited tungsten silicide layer is removed by introducing a large quantity of SiH.sub.4 gas into the chamber. Again the tungsten silicide layer is secondarily deposited, thinner than desired in the device, on the tungsten silicide layer from which the fluorine is removed and, thereafter, the fluorine contained in the secondarily deposited tungsten silicide layer is removed by introducing a large quantity of SiH.sub.4 gas. Such a process is repeated until the tungsten silicide layer of the thickness desired in the device is deposited.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: A process is provided for making a package-type fused solid electrolytic capacitor. In the process, a capacitor element having a chip body and an anode wire is first mounted between an opposed pair of anode and cathode leads with the anode wire attached to the anode lead, the cathode lead having a tip cutout. Then, a material fuse wire is connected to the chip body and the cathode lead with an intermediate portion of the material fuse wire located in the tip cutout of the cathode lead. Then, a resin package is molded to enclose the capacitor element together with the material fuse wire. Then, the resin package is separated from the anode and cathode leads by cutting. Then, an anode terminal electrode and a cathode terminal electrode are formed on the resin package in electrical conduction with the anode wire and the fuse wire, respectively.